參數(shù)資料
型號(hào)： IA8X44
廠商： Innovasic Semiconductor
英文描述： SDLC COMMUNICATIONS CONTROLLER
中文描述： SDLC的通信控制器
文件頁(yè)數(shù)： 17/49頁(yè)
文件大?。?/td> 220K
代理商： IA8X44
IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER
TMOD.1
M1
Timer 0 mode selector bit.
TMOD.2
C/T
C/T Selects Timer0 or Counter0 operation. When set to 1,
the Counter operation is performed, when cleared to 0, the
register will function as a Timer.
TMOD.3
GATE
If set, enables external gate control for counter/timer0 (pin
INT0/ for Counter 0). When INT0/ is high, and TR0 bit is
set (see TCON register), the counter is incremented every
falling edge on T0 input pin.
TMOD.4
M0
Timer 1 mode selector bit.
TMOD.5
M1
Timer 1 mode selector bit.
TMOD.6
C/T
C/T Selects Timer1 or Counter1 operation. When set to 1,
the Counter operation is performed, when cleared to 0, the
register will function as a Timer.
TMOD.7
GATE
If set, enables external gate control for counter/timer1 (pin
INT1/ for Counter 1). When INT1/ is high, and TR1 bit is
set (see TCON register), the counter is incremented every
falling edge on T1 input pin..
Timer Mode Select Bits
M1 M0 Operating Mode
0
0
0
13 bit timer
0
1
1
16 bit timer/counter
1
0
2
8 bit auto-reload timer/counter
1
1
3
Timer0 – TL0 is a standard 8-bit timer/counter
controlled by timer 0 control bits. TH0 is an 8-bit
timer function only, controlled by timer 1 control bits.
1
1
3
Timer/counter1 stopped and holds its count. Can be
used to start/stop timer 1 when timer 0 is in mode 3.
Timer Control (TCON):
The Timer Control register provides control bits that start and stop the counters. It also contains
bits to select the type of external interrupt desired, edge or level. Additionally TCON contains
status bits showing when a timer overflows and when an interrupt edge has been detected.
TCON
Bit: 7
6
5
4
TF1
TR1
TF0
TR0
TCON.0
IT0
Interrupt 0 type control bit. Selects falling edge or low level
on input pin to cause interrupt.
TCON.1
IE0
Interrupt 0 edge flag. Set by hardware, when falling edge on
external pin INT1/ is observed. Cleared when interrupt is
processed.
TCON.2
IT1
Interrupt 1 type control bit. Selects falling edge or low level
on input pin to cause interrupt.
Copyright
2003
innov
ASIC
The End of Obsolescence
ENG210010112-00
www.innovasic.com
Customer Support:
Page 17 of 49
1-888-824-4184
3
2
1
0
IE1
IT1
IE0
IT0
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