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| 型號： | HYMD18M645AL6-K |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | 67.60 X 31.75 X 1 MM, SODIMM-200 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 232K |
| 代理商： | HYMD18M645AL6-K |
HYMD18M645A(L)6-K/H/L
Rev. 0.5/May. 02
10
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
For command/address input slew rate >=1.0V/ns
4.
For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
5.
CK, /CK slew rates are >=1.0V/ns
6.
These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH)
Parameter
Symbol
-K(DDR266A)
-H(DDR266B)
-L(DDR200)
Unit
Note
Min
Max
Min
Max
Min
Max
Write DQS High Level Width
tDQSH
0.35
-
0.35
-
0.35
-
CK
Write DQS Low Level Width
tDQSL
0.35
-
0.35
-
0.35
-
CK
Clock to First Rising edge of DQS-In
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.5-0.5-
0.6-
ns
6,7,
11~13
Data-in Hold Time to DQS-In (DQ & DM)
tDH
0.5-0.5-
0.6-
ns
DQ & DM Input Pulse Width
tDIPW
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
tWPRES
0-0
-
0-
CK
Write DQS Preamble Hold Time
tWPREH
0.25
-
0.25
-
0.25
-
CK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
tMRD
2-2
-
2-
CK
Exit Self Refresh to Any Execute Command
tXSC
200
-
200
-
200
-
CK
8
Average Periodic Refresh Interval
tREFI
-
15.6
-
15.6
-
15.6
us
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
0.5
0
0.4
+50
0
0.3
+100
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYMD18M645AL6-L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|8MX64|CMOS|DIMM|200PIN|PLASTIC |
| HYMD18M725A6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72|2.5V|K/H/L|x5|DDR SDRAM - SO DIMM 64MB |
| HYMD18M725A6-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|8MX72|CMOS|DIMM|200PIN|PLASTIC |
| HYMD18M725A6-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|8MX72|CMOS|DIMM|200PIN|PLASTIC |
| HYMD18M725A6-L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|8MX72|CMOS|DIMM|200PIN|PLASTIC |
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