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參數(shù)資料
| 型號： | HYMD18M645AL6-K |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 8M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | 67.60 X 31.75 X 1 MM, SODIMM-200 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 232K |
| 代理商： | HYMD18M645AL6-K |
HYMD18M645A(L)6-K/H/L
Rev. 0.5/May. 02
8
DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-K
-H
-L
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
600
560
mA
Operating Current
IDD1
One bank; Active - Read - Precharge ;
Burst Length=2; tRC=tRC(min); tCK=tCK(min) ;
address and control inputs changing once per clock
cycle
600
560
mA
Precharge Power Down
Standby Current
IDD2P
All banks idle; Power down mode ; CKE=Low,
tCK= tCK(min)
80
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing
once per clock cycle.
VIN=VREF for DQ, DQS, and DM
160
140
mA
Active Power Down
Standby Current
IDD3P
One bank active ; Power down mode ; CKE=Low,
tCK=tCK(min)
100
mA
Active Standby Current
IDD3N
/CS= HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC = tRAS(max); tCK= tCk(min);
DQ, DM, and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle
280
200
mA
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
800
720
mA
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM, and DQS
inputs changing twice per clock cycle
1000
920
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
880
800
Self Refresh Current
IDD6
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Normal
8mA
Low Power
4mA
Operating Current - Four
Bank Operation
IDD7
Four bank interleaving with BL=4, Refer to the
following page for detailed test condition
1300
1200
mA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYMD18M645AL6-L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|8MX64|CMOS|DIMM|200PIN|PLASTIC |
| HYMD18M725A6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72|2.5V|K/H/L|x5|DDR SDRAM - SO DIMM 64MB |
| HYMD18M725A6-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|8MX72|CMOS|DIMM|200PIN|PLASTIC |
| HYMD18M725A6-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|8MX72|CMOS|DIMM|200PIN|PLASTIC |
| HYMD18M725A6-L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|8MX72|CMOS|DIMM|200PIN|PLASTIC |
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