- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370795 > HYE25L256160AC-8 (INFINEON TECHNOLOGIES AG) 256-Mbit Mobile-RAM PDF資料下載
參數(shù)資料
| 型號： | HYE25L256160AC-8 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit Mobile-RAM |
| 中文描述： | 256兆移動RAM |
| 文件頁數(shù)： | 16/55頁 |
| 文件大小： | 1053K |
| 代理商： | HYE25L256160AC-8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
HYE25L256160AC
256-Mbit Mobile-RAM
Functional Description
Data Sheet
16
V1.1, 2003-04-16
Deselect
The Deselect function prevents new commands from being executed by the 256-Mbit Mobile-RAM. Operations
already in progress are not affected.
No Operation (NOP)
The No Operation (NOP) command is used to perform a NOP to a 256-Mbit Mobile-RAM. This prevents unwanted
commands from being registered during idle or wait states. Operations already in progress are not affected.
Mode Register Set
The mode registers are loaded via inputs A12-A0, BA1 and BA0. See mode register descriptions in
Chapter 3.2
.
The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A
subsequent executable command cannot be issued until
t
MRD
is met.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access. This is called
the start of a RAS cycle and occures when RAS is low and both CAS and WE are high at the positive edge of the
clock. The value on the BA1 and BA0 inputs selects the bank, and the address provided on inputs A12-A0 selects
the row. This row remains active (or open) for accesses until a Precharge (or Read or Write with Auto Precharge)
is issued to that bank. A Precharge (or Read or Write with Auto Precharge) command must be issued and
completed before opening a different row in the same bank.
Read and Write
A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay,
t
RCD
, from
the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations
are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the burst length programmed at the
mode set operation, which is one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length
and serial data accesses are done within this boundary. The first column address to be accessed is supplied at
the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and
its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest
of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O
organisation and column addressing. Full page burst operation does not self terminate once the burst length has
been reached. In other words, unlike burst length of 2, 4 and 8, full page burst continues until it is terminated using
another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address are
possible once the RAS cycle latches the sense amplifiers. The maximum
t
RAS
or the refresh interval time limits the
number of random column accesses. A new burst access can be done even before the previous burst ends. The
interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining
addresses are overridden by the new address with the full burst length. An interrupt which accompanies an
operation change from a read to a write is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With
the programmed burst length, alternate access and precharge operations on two or more banks can realize fast
serial data access modes among many different pages. Once two or more banks are activated, column to column
interleave operation can be performed between different pages. When the partial array activation is set, data will
get lost when self-refresh is used in all non activated banks.
The Read command is used to initiate a burst read access to an active (open) row. The value on the BA1 and BA0
inputs selects the bank, and the address provided on inputs A9-A0 for x16 selects the starting column location.
The value on input A10/AP determines whether or not Auto Precharge is used. If Auto Precharge is selected, the
row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains
open for subsequent accesses.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYE25L256160AF | 256MBit Mobile-RAM |
| HYE25L256160AF-75 | CAP TANT 10UF 6.3V 20% SMD |
| HYE25L256160AC-7.5 | BJAWBMSpecialty DRAMs Mobile-RAM |
| HYM321000GS-60 | 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module |
| HYM321000S-60 | 1M x 32-Bit Dynamic RAM Module 2M x 16-Bit Dynamic RAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYE25L256160AF | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256MBit Mobile-RAM |
| HYE25L256160AF-7.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:BJAWBMSpecialty DRAMs Mobile-RAM |
| HYE25L256160AF-75 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256MBit Mobile-RAM |
| HYESD0514P | 制造商:HY 制造商全稱:HY ELECTRONIC CORP. 功能描述:4 Channel Low Capacitance ESD Protection Diode Array |
發(fā)布緊急采購，3分鐘左右您將得到回復。