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參數(shù)資料
| 型號： | HYE18P32161AC-85 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 32M Asynchronous/Page CellularRAM |
| 中文描述： | 32M的異步/頁的CellularRAM |
| 文件頁數(shù)： | 18/33頁 |
| 文件大?。?/td> | 641K |
| 代理商： | HYE18P32161AC-85 |
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HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Functional Description
Data Sheet
18
V2.0, 2003-12-16
Figure 8
PASR Configuration Example
2.3.2
To put the device in deep power down mode, it is required to comply with 2-steps. At first, the DPD mode bit must
be set to be enabled in the Refresh Configuration Register. When DPD entry is really required, ZZ pin must be
asserted to low for longer than 10μs. Between these 2 steps, any normal operations are permitted. Once the
device enters into this extreme low power mode, current consumption is cut down to less than 25μA.
All internal voltage generators inside the CelllularRAM are switched off and the internal self-refresh is stopped.
This means that all stored information will be lost in any time. The device will remain in DPD mode as long as ZZ
is held low.To exit the Deep Power Down mode, it is needed to simply bring ZZ to high voltage level. A guard time
of at least 150μs has to be met where no commands beside DESELECT must be applied to re-enter standby or
idle mode. (see
Figure 16
).
Deep Power Down Mode
2.3.3
The 2-bit wide TCSR field features four different temperature ranges to adjust the refresh period to the actual case
temperature. DRAM technology requires higher refresh rates at higher temperature. At low temperature the
refresh rate can be reduced, which reduces as well the standby current of the chip. This feature can be used in
addition to PAR to lower power consumption in case of low or medium temperatures. Please refer to
Table 5
.
Temperature Compensated Self Refresh (TCSR)
2.3.4
Table 5
demonstrates the currents in standby mode when PASR, TCSR or DPD is applied.
Power Saving Potential in Standby When Applying PASR, TCSR or DPD
Table 5
Operation
Mode
NO
OPERATION/
DESELECT
Standby Currents When Applying PASR, TCSR or DPD
Power Mode
PASR
Bit
Controlled
RCR.Bit6-5
RCR.Bit2-0
Wake-Up
Phase
–
–
Active
Array
–
Full
1/2
1/4
1/8
0
0
Standby [
μ
A]
STANDBY
TCSR
PASR
85°
90(120)
80(105)
70(90)
60(75)
50(60)
70°
75(100)
68(90)
62(80)
55(70)
50(60)
45°
60(80)
56(75)
53(70)
52(65)
50(60)
15°
50(60)
50(60)
50(60)
50(60)
50(60)
DPD
DEEP POWER
DOWN
DPD
RCR.Bit4
~150
μ
s
25.0
24Mb
Deactivated
000000h
07FFFFh
RCR.Bit 2,1,0= 010
Active Memory
Array defined by
PASR to 8Mb
8M
Activated
32Mb CellularRAM
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| HYE18P32161AC | 32M Asynchronous/Page CellularRAM |
| HYE18P32161ACL70 | JT 23C 21#20 2#16 SKT PLUG |
| HYE18P32161ACL85 | Circular Connector; MIL SPEC:MIL-DTL-38999 Series II; Body Material:Metal; Series:JT; No. of Contacts:11; Connector Shell Size:18; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
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相關代理商/技術參數(shù) |
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| HYE18P32161ACL70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Asynchronous/Page CellularRAM |
| HYE18P32161ACL85 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:32M Asynchronous/Page CellularRAM |
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