參數(shù)資料
型號(hào)： HYB25D256160BTL-7F
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit Double Data Rate SDRAM, Die Rev. B
中文描述： 256兆雙倍數(shù)據(jù)速率SDRAM，模具版本B
文件頁數(shù)： 61/77頁
文件大?。?/td> 1779K
代理商： HYB25D256160BTL-7F
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Page 61 of 77
2003-01-09, V1.1
t
RPRE
Read preamble
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
1-4
t
RPST
Read postamble
0.40
0.60
0.40
0.60
0.40
0.60
0.40
0.60
t
CK
1-4
t
RAS
Active to Precharge command
50
120,000
45
120,000
45
120,000
42
70,000
ns
1-4
t
RC
Active to Active/Auto-refresh command
period
70
65
60
60
ns
1-4
t
RFC
Auto-refresh to Active/Auto-refresh com-
mand period
80
75
75
72
ns
1-4
t
RCD
Active to Read or Write delay
20
20
15
18
ns
1-4
t
RP
Precharge command period
20
20
15
18
ns
1-4
t
RAP
Active to Autoprecharge delay
20
20
20
18
ns
1-4
t
RRD
Active bank A to Active bank B command
15
15
15
12
ns
1-4
t
WR
Write recovery time
15
15
15
15
ns
1-4
t
DAL
Auto precharge write recovery
+ precharge time
(twr/tck) + (trp/tck)
t
CK
1-4,9
t
WTR
Internal write to read command delay
1
1
1
1
t
CK
1-4
t
XSNR
Exit self-refresh to non-read command
80
75
75
75
ns
1-4
t
XSRD
Exit self-refresh to read command
200
200
200
200
t
CK
1-4
t
REFI
Average Periodic Refresh Interval (8192
refresh commands per 64ms refresh
period)
7.8
7.8
7.8
7.8
s
1-4, 8
1. Input slew rate >= 1V/ns for DDR266 & DDR333 and = 1V/ns for DDR 200
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other
than CK/CK, is V
REF.
CK/CK slew rate are >= 1.0 V/ns
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
TT
.
5. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage
level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance
(bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is
defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS
will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at
this time, depending on t
DQSS
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
10. These parameters guarantee device timing, but they are not necessarilty tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ns, measured between
VOH(ac) and VOL(ac)
Electrical Characteristics & AC Timing - Absolute Specifications
(0 C T
A
70 C V
DDQ
= 2.5V 0.2V; V
DD
= 2.5V 0.2V)
(Part 2 of 2)
Symbol
Parameter
DDR200
-8
DDR266A
-7
DDR266
-7F
DDR333
-6
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
相關(guān)PDF資料
PDF描述
HYB25D256160BTL-8 256-Mbit Double Data Rate SDRAM, Die Rev. B
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D256160BTL-8 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM
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HYB25D256160CE-5 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM
HYB25D256160CE-5A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM
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