參數(shù)資料
型號(hào)： HYB25D256160BTL-7F
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit Double Data Rate SDRAM, Die Rev. B
中文描述： 256兆雙倍數(shù)據(jù)速率SDRAM，模具版本B
文件頁(yè)數(shù)： 57/77頁(yè)
文件大?。?/td> 1779K
代理商： HYB25D256160BTL-7F
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Page 57 of 77
2003-01-09, V1.1
IDD Specification and Conditions
(0 C T
A
70 C V
DDQ
= 2.5V 0.2V; V
DD
= 2.5V 0.2V)
Notes
typ.
max.
typ.
max.
typ.
max.
typ.
max.
4
x4/x8
70
90
75
100
83
110
85
110
mA
x16
72
95
77
105
86
115
88
115
mA
x4/x8
80
100
90
110
98
120
100
120
mA
x16
83
105
94
115
102
125
104
125
mA
IDD2P
5
7
6
8
6
8
6
9
mA
1, 2
IDD2F
30
35
35
40
35
40
45
55
mA
1, 2
IDD2Q
18
22
20
25
20
25
25
28
mA
1, 2
IDD3P
13
16
15
18
15
18
18
21
mA
1, 2
x4/x8
40
45
50
55
50
55
60
65
mA
x16
42
50
52
60
52
60
63
70
mA
x4/x8
79
95
95
115
95
115
110
140
mA
x16
89
110
107
130
107
130
124
160
mA
x4/x8
85
105
105
125
105
125
125
145
mA
x16
96
120
119
140
119
140
141
165
mA
IDD5
126
170
135
180
135
180
144
190
mA
1, 2
standard version
1.5
2.5
1.5
2.5
1.5
2.5
1.5
2.5
mA
low power version
1.20
1.25
1.20
1.25
1.20
1.25
1.20
1.25
mA
x4/x8
150
210
171
225
171
225
208
270
x16
158
220
180
235
180
235
218
285
1. IDD specifications are tested after the device is properly initialized and measured
at 100 MHz for DDR200, 133 MHz for DDR266(A) and 166 MHz for DDR333
2. Input slew rate = 1V/ns.
3. Enables on-chip refresh and address counters
4. Test condition for typical values : VDD = 2.5V ,Ta = 25°C, test condition for maximum values: test limit at VDD = 2.7V ,Ta = 10°C
1, 2
IDD1
Operating Current
: one bank; active/read/precharge;
burst length 4;
Refer to the following page for detailed test conditions.
Precharge Floating Standby Current
: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; address and other control inputs changing once per clock cycle, VIN
= VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
: /CS >= VIH MIN, all banks idle;
CKE >= VIH MIN; address and other control inputs stable
at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM.
Auto-Refresh Current
: tRC = tRFC MIN, distributed refresh
IDD6
Self-Refresh Current
: CKE <= 0.2V; external clock on
IDD7
Operating Current
: four bank; four bank interleaving with burst
length 4;
Refer to the following page for detailed test conditions.
IDD4R
Operating Current
: one bank active; BL2; reads; continuous burst;
address and control inputs changing once per clock cycle; 50% of
data outputs changing on every clock edge; CL2 for DDR200 and
DDR266(A), CL3 for DDR333 and DDR400; IOUT = 0mA
Operating Current
: one bank active; Burst = 2; writes; continuous
burst; address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge; CL2 for
DDR200 and DDR266(A), CL3 for DDR333 and DDR400
IDD3N
IDD4W
Active Standby Current
: one bank active; CS >= VIH MIN;
CKE >= VIH MIN; tRC = tRAS MAX; DQ, DM, and DQS inputs
changing twice per clock cycle; address and control inputs
changing once per clock cycle
Active Power-Down Standby Current
: one bank active; power-down mode;
CKE <= VIL MAX; VIN = VREF for DQ, DQS and DM.
Precharge Power-Down Standby Current
: all banks idle; power-down mode;
CKE <= VIL MAX
Operating Current
: one bank; active / precharge; tRC = tRC MIN;
DQ, DM, and DQS inputs changing once per clock cycle; address
and control inputs changing once every two clock cycles
1, 2
IDD0
Symbol Parameter/Condition
Unit
DDR200
-8
DDR266A
-7
DDR266
-7F
DDR333
-6
1, 2, 3
mA
1, 2
1, 2
1, 2
1, 2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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HYB25D256160CE-5 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM
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