參數(shù)資料
型號(hào)： HYB25D256160BTL-7F
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit Double Data Rate SDRAM, Die Rev. B
中文描述： 256兆雙倍數(shù)據(jù)速率SDRAM，模具版本B
文件頁(yè)數(shù)： 46/77頁(yè)
文件大?。?/td> 1779K
代理商： HYB25D256160BTL-7F
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Page 46 of 77
2003-01-09, V1.1
Truth Table 2: Clock Enable (CKE)
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Current State
CKE n-1
CKEn
Command n
Action n
Notes
Previous
Cycle
Current
Cycle
Self Refresh
L
L
X
Maintain Self-Refresh
Self Refresh
L
H
Deselect or NOP
Exit Self-Refresh
1
Power Down
L
L
X
Maintain Power-Down
Power Down
L
H
Deselect or NOP
Exit Power-Down
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry
All Banks Idle
H
L
AUTO REFRESH
Self Refresh Entry
Bank(s) Active
H
L
Deselect or NOP
Active Power-Down Entry
H
H
See “Truth Table 3: Current State
Bank n - Command to Bank n
(Same Bank)” on page 47
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t
XSNR
) period. A mini-
mum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
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HYB25D256160BTL-8 256-Mbit Double Data Rate SDRAM, Die Rev. B
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D256160BTL-8 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM
HYB25D256160CC-5 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM
HYB25D256160CC-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM
HYB25D256160CE-5 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM
HYB25D256160CE-5A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM
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