- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370783 > HYB25D128323C-4.5 (INFINEON TECHNOLOGIES AG) 128 Mbit DDR SGRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | HYB25D128323C-4.5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit DDR SGRAM |
| 中文描述： | 128兆的DDR SGRAM |
| 文件頁數(shù)： | 32/53頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | HYB25D128323C-4.5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
32
V1.7, 2003-07
interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears. Read
to Read interval (CAS#(a) to CAS#(b) Command period,
t
CCD
) is minimum 1 CLK.
Figure 24
Read interrupted by Read
3.6.2
To interrupt a burst read with a write command, a Burst Stop command must be asserted to avoid data contention
on the I/O bus by placing the DQ's (Output drivers) in a high impedance state at least one clock cycle before the
Write Command is initiated (Last Output to Write Command Latency). To insure that the DQs are tri-stated one
cycle before the write operation begins, the Burst Stop command must be applied at least 3 clock cycles for CL =
2, at least 4 clock cycles for CL = 3 or at least 5 clock cycles for CL = 4 before the Write command.
Read Interrupted by a Write
Figure 25
Read interrupted by Write
CLK
READ a
DQSx
DQx
D-out
a0
Command
READ b
NOP
NOP
NOP
NOP
D-out
a1
D-out
b1
tCCD
Burst length = 4
CL = 2
D-out
b0
D-out
b3
D-out
b2
CLK
READ
DQSx
DQx
D-out
0
Command
BST
NOP
NOP
WRITE
NOP
D-out
1
D-in
1
Burst length = 4
CL = 2
D-in
0
D-in
3
D-in
2
Burst Stop to Write command latency
NOP
NOP
Burst Stop latency = CL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D128323C-5 | 128 Mbit DDR SGRAM |
| HYB25D128323C-L4.5 | 128 Mbit DDR SGRAM |
| HYB25D128323CL4.5 | 128 Mbit DDR SGRAM |
| HYB25D128323C-L3.6 | 128 Mbit DDR SGRAM |
| HYB25D128323ACL-33 | JT 55C 55#22D SKT PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128323C-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL3.6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323C-L3.6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL-3.6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。