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參數(shù)資料
| 型號： | HYB25D128323C-4.5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit DDR SGRAM |
| 中文描述： | 128兆的DDR SGRAM |
| 文件頁數(shù)： | 31/53頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | HYB25D128323C-4.5 |
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Data Sheet
31
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Figure 23
Write Burst with Auto Precharge
Note:
t
WR
starts at the first rising edge of clock after the last valid edge of the 4 DQSx.
When Write with Auto Precharge is asserted, new commands can be asserted at T3.. T8 as shown in
Table 8
.
An Interrupt of a running WRITE burst with Auto Precharge i.e. at T3 to the same bank with another WRITE+AP
command is allowed as long as the burst is running, it will extend the begin of the internal Precharge operation to
the last WRITE+AP command.
Interrupts of a running WRITE burst with Auto Precharge i.e. at T3 are not allowed when doing concurrent
WRITE’s to another active bank. Consecutive WRITE or WRITE+AP bursts (T4.. T7) to other open banks are
possible. ACTIVATE or PRECHARGE commands to another bank are always possible while a WRITE with Auto
Precharge operation is in progress.
3.6
Burst Interruption
3.6.1
A Burst Read can be interrupted before completion of the burst by a new Read command given to any bank. When
the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read command continues to appear on the outputs until the CAS latency from the
Read Interrupted by a Read
Table 8
Asserted
Command
Concurrent Write Auto Precharge Support
For same Bank
T3
T4
T5
NO
NO
NO
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
PRECHARGE
NO
NO
For different Bank
T3
T4
NO
YES
NO
YES
NO
NO
NO
NO
YES
YES
YES
YES
T6
NO
NO
NO
NO
NO
NO
T7
NO
NO
NO
NO
NO
NO
T8
NO
NO
NO
NO
NO
NO
T5
YES
YES
NO
NO
YES
YES
T6
YES
YES
NO
NO
YES
YES
T7
YES
YES
YES
YES
YES
YES
WRITE
WRITE+AP
READ
READ+AP
ACTIVATE
NO
WRITE A
+ AP
CLK
BANK A
ACTIVATE
Command
NOP
NOP
NOP
NOP
Burst length = 4
DQSx
DQx
D-in
0
D-in
1
D-in
2
D-in
3
Begin of
Auto Precharge
BL / 2
NOP
NOP
NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
t RAS(min)
t RP
t WR
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| HYB25D128323C-5 | 128 Mbit DDR SGRAM |
| HYB25D128323C-L4.5 | 128 Mbit DDR SGRAM |
| HYB25D128323CL4.5 | 128 Mbit DDR SGRAM |
| HYB25D128323C-L3.6 | 128 Mbit DDR SGRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128323C-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL3.6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323C-L3.6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL-3.6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
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