參數(shù)資料
型號(hào)： HYB25D128323C-4.5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit DDR SGRAM
中文描述： 128兆的DDR SGRAM
文件頁(yè)數(shù)： 25/53頁(yè)
文件大?。?/td> 1166K
代理商： HYB25D128323C-4.5
Data Sheet
25
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Figure 17
Burst Read Operation
3.5.11
The Burst Write is initiated by issuing a WRITE command at the rising edge of the clock. The address inputs (A7..
A0) determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on
the first rising edge of DQSx following the WRITE command. The time between the WRITE command and the first
corresponding edge of the data strobe is
t
DQSS
. The remaining data inputs must be supplied on each subsequent
rising and falling edge of the data strobe until the burst length is completed. When the burst has been finished,
any additional data supplied to the DQ pins will be ignored.
Burst Write Operation (WRITE)
CLK
Read
DQSx
DQx
Command
CL = 2
NOP
NOP
NOP
NOP
NOP
NOP
Read
Preamble
NOP
D-out
0
D-out
1
D-out
2
D-out
3
Burst length = 4
DQSx
DQx
D-out
0
D-out
1
D-out
2
D-out
3
Read
Postamble
CAS latency = 2
CAS latency = 3
CL = 3
Read
Preamble
Read
Postamble
DQSx
DQx
CAS latency = 4
CL = 4
D-out
0
D-out
1
D-out
2
D-out
3
Read
Preamble
Read
Postamble
相關(guān)PDF資料
PDF描述
HYB25D128323C-5 128 Mbit DDR SGRAM
HYB25D128323C-L4.5 128 Mbit DDR SGRAM
HYB25D128323CL4.5 128 Mbit DDR SGRAM
HYB25D128323C-L3.6 128 Mbit DDR SGRAM
HYB25D128323ACL-33 JT 55C 55#22D SKT PLUG
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D128323C-5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323CL3.6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323C-L3.6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323CL-3.6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323CL4.5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
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