參數(shù)資料
型號(hào)： HYB18L256160BF-75
廠商： INFINEON TECHNOLOGIES AG
英文描述： DRAMs for Mobile Applications
中文描述： 針對(duì)移動(dòng)應(yīng)用的DRAM
文件頁(yè)數(shù)： 31/49頁(yè)
文件大?。?/td> 1327K
代理商： HYB18L256160BF-75
Data Sheet
31
V1.4, 2004-04-30
HY[B/E]18L256160B[C/F]-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.6.1
Data from any WRITE burst may be truncated using the BURST TERMINATE command (see
Page 33
), provided
that Auto Precharge was not activated. The input data provided coincident with the BURST TERMINATE
command will be ignored. This is shown in
Figure 30
. The BURST TERMINATE command may be used to
terminate a full-page WRITE which does not self-terminate.
WRITE Burst Termination
Figure 30
Terminating a WRITE Burst
2.4.6.2
Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long
as CKE is registered LOW, the following internal clock pulse(s) will be ignored and no data will be captured, as
shown in
Figure 31
.
Clock Suspend Mode for WRITE Cycles
Figure 31
Clock Suspend Mode for WRITE Bursts
Ba A, Col n = Bank A, Column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
2 subsequent elements of Data In are written in the programmed order following DI n.
The burst is terminated after the 3rd data element.
= Don't Care
CLK
Command
NOP
NOP
BST
NOP
NOP
WRITE
NOP
Address
Ba A,
Col n
DQ
DI n
DI n+1
DI n+2
Ba A, Col n etc. = Bank A, Column n etc.
DO n etc. = Data Out from column n etc.
CL = 2 in the case shown
Clock suspend latency t
CSL
is 1 clock cycle
CLK
CKE
internal
clock
Command
NOP
NOP
NOP
WRITE
NOP
Ba A,
Col n
Address
DQ
DI n+2
DI n
DI n+1
= Don't Care
t
CSL
t
CSL
t
CSL
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