參數(shù)資料
型號(hào)： HY5R256HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 256M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 256M
文件頁(yè)數(shù)： 63/64頁(yè)
文件大?。?/td> 4542K
代理商： HY5R256HC
Rev.0.9 / Dec.2000
63
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
NOXOP
No-operation command in XOP field.
NSR
INIT register field- NAP self-refresh.
packet
A collection of bits carried on the Channel.
PDN
Power state - needs SCK/CMD wakeup.
PDNR
Powerdown command in ROP field.
PDNXA
Control register - PDN exit delay A.
PDNXB
Control register - PDN exit delay B.
pin efficiency
The fraction of non-idle cycles on a pin.
PRE
PREC,PRER,PREX precharge commands.
PREC
Precharge command in COP field.
precharge
Prepares sense amp and bank for activate.
PRER
Precharge command in ROP field.
PREX
Precharge command in XOP field.
PSX
INIT register field - PDN/NAP exit.
PSR
INIT register field - PDN self-refresh.
PVER
CNFGB register field - protocol version.
Q
Read data packet on DQ pins.
R
Row address field of ROWA packet.
RBIT
CNFGB register field - # row address bits.
RD/RDA
Read (/precharge) command in COP field.
read
Operation of accesssing sense amp data.
receive
Moving information from the Channel into
the RDRAM (a serial stream is demuxed).
REFA
Refresh-activate command in ROP field.
REFB
Control register - next bank (self-refresh).
REFBIT
CNFGA register field - ignore bank bits
(for REFA and self-refresh).
REFP
Refresh-precharge command in ROP field.
REFR
Control register - next row for REFA.
refresh
Periodic operations to restore storage cells.
retire
The automatic operation that stores write
buffer into sense amp after WR command.
RLX
RLXC,RLXR,RLXX relax commands.
RLXC
Relax command in COP field.
RLXR
Relax command in ROP field.
RLXX
Relax command in XOP field.
ROP
Row-opcode field in ROWR packet.
2
CBIT
dualocts of cells (bank/sense amp).
row
ROW
Pins for row-access control
ROW
ROWA or ROWR packets on ROW pins.
ROWA
Activate packet on ROW pins.
ROWR
Row operation packet on ROW pins.
RQ
Alternate name for ROW/COL pins.
RSL
Rambus Signaling Levels.
SAM
Sample (I
OL
) command in XOP field.
Serial address packet for control register
transactions w/ SA address field.
SA
SBC
Serial broadcast field in SRQ.
SCK
CMOS clock pin..
SD
Serial data packet for control register
transactions w/ SD data field.
SDEV
Serial device address in SRQ packet.
SDEVID
INIT register field - Serial device ID.
self-refresh
Refresh mode for PDN and NAP.
sense amp
Fast storage that holds copy of bank’s row.
SETF
Set fast clock command from SOP field.
SETR
Set reset command from SOP field.
SINT
Serial interval packet for control register
read/write transactions.
SIO0,SIO1
CMOS serial pins for control registers.
SOP
Serial opcode field in SRQ.
SRD
Serial read opcode command from SOP.
SRP
INIT register field - Serial repeat bit.
SRQ
Serial request packet for control register
read/write transactions.
STBY
Power state - ready for ROW packets.
SVER
Control register - stepping version.
SWR
Serial write opcode command from SOP.
TCAS
TCLSCAS register field - t
CAS
core delay.
TCLSCAS register field - t
CLS
core delay.
Control register - t
CAS
and t
CLS
delays.
Control register - t
CYCLE
delay.
Control register - t
DAC
delay.
Control register - for test purposes.
TCLS
TCLSCAS
TCYCLE
TDAC
TEST77
TEST78
Control register - for test purposes.
TRDLY
Control register - t
RDLY
delay.
ROW,COL,DQ packets for memory
access.
transaction
transmit
Moving information from the RDRAM
onto the Channel (parallel word is muxed).
WR/WRA
Write (/precharge) command in COP field.
write
Operation of modifying sense amp data.
XOP
Extended opcode field in COLX packet.
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