參數(shù)資料
型號(hào)： HY5R256HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 256M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 256M
文件頁(yè)數(shù)： 52/64頁(yè)
文件大小： 4542K
代理商： HY5R256HC
52
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
RSL - Receive Timing
Figure 55: is a timing diagram which shows the detailed
requirements for the RSL input signals on the Channel.
The DQA, DQB, ROW, and COL signals are inputs which
receive information transmitted by a Direct RAC on the
Channel. Each signal is sampled twice per t
CYCLE
interval.
The set/hold window of the sample points is t
S
/t
H.
The
sample points are centered at the 0% and 50% points of a
cycle, measured relative to the crossing points of the falling
CFM clock edge. The set and hold parameters are measured
at the V
REF
voltage point of the input transition.
The t
DR
and t
DF
rise- and fall-time parameters are measured
at the 20% and 80% points of the input transition.
Figure 55: RSL Timing - Data Signals for Receive
V
DIH
V
REF
V
DIL
80%
20%
V
CIH
50%
V
CIL
80%
20%
CFM
CFMN
DQA
t
S
ROW
DQB
t
DF
t
DR
t
H
t
S
t
H
0.5t
CYCLE
even
odd
COL
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