- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370740 > HY5R256HC -|2.5V|8K|40|Direct RDRAM - 256M PDF資料下載
參數(shù)資料
| 型號： | HY5R256HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 256M |
| 中文描述： | - |為2.5V | 8K的| 40 |直接RDRAM的- 256M |
| 文件頁數(shù)： | 35/64頁 |
| 文件大小： | 4542K |
| 代理商： | HY5R256HC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Rev.0.9 / Dec.2000
35
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
.
Figure 36: NAPX Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Control Register: NAPX
Address: 045
16
Read/write register.
Reset value is undefined
Note : t
SCYCLE
is t
CYCLE1
(SCK cycle time)
NAPXA4..0 - Nap Exit Phase A. This field specifies
the number of SCK cycles during the first phase for
exiting NAP mode. It must satisfy:
NAPXAt
SCYCLE
> t
NAPXA,MAX
Do not set this field to zero.
0
0
0
0
0
DQS
NAPXA4..0
NAPX4..0
NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK
cycles during the first plus second phases for exiting NAP mode. It must satisfy:
NAPXt
SCYCLE
> t
NAPXA,MAX
+t
NAPXB,MAX
Do not set this field to zero.
DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5
cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device
selection on DQ5..0.
Figure 37: PDNXA Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined
PDNXA4..0 - PDN Exit Phase A. This field specifies
the number of (64SCK cycle) units during the first
phase for exiting PDN mode. It must satisfy:
PDNXA64t
SCYCLE
> t
PDNXA,MAX
Do not set this field to zero.
Note - only PDNXA5..0 are implemented.
Control Register: PDNXA
Address: 046
16
0
0
0
PDNXA12..0
Figure 38: PDNX Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined
PDNX4..0 - PDN Exit Phase A plus B. This field spec-
ifies the number of (256SCK cycle) units during the
first plus second phases for exiting PDN mode. It must
satisfy:
PDNX256t
SCYCLE
> PDNXA64t
SCYCLE
+
t
PDNXB,MAX
If this cannot be satisfied, then the maximum PDNX
value should be written, and the t
S4
/t
H4
timing window
will be modified (see Figure 49:).
Do not set this field to zero.
Note - only PDNX2..0 are implemented.
Control Register: PDNX
Address: 047
16
0
0
0
PDNX12..0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5R288HC | -|2.5V|8K|40|Direct RDRAM - 288M |
| HY5V16CF | 1Mx16|3.3V|4K|H|SDR SDRAM - 16M |
| HY5V16CF-H | x16 SDRAM |
| HY5V16CF-S | x16 SDRAM |
| HY6116-10 | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5S2B6DLF-BE | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLFP-BE | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLFP-SE | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S2B6DLF-SE | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
| HY5S5B2BLF-6E | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M (8Mx32bit) Mobile SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。