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參數(shù)資料
| 型號： | HY5DU12422BLT-H |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 128M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 6/31頁 |
| 文件大?。?/td> | 686K |
| 代理商： | HY5DU12422BLT-H |
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Rev. 1.1 / Apr. 2006
14
1HY5DU12422B(L)T
HY5DU12822B(L)T
HY5DU121622B(L)T
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and
CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until reset by another MRS command.
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
Operating Mode
CAS Latency
BT
Burst Length
A2
A1
A0
Burst Length
Sequential
Interleave
0
Reserved
001
2
010
4
011
8
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
A3
Burst Type
0
Sequential
1Interleave
A6
A5
A4
CAS Latency
000
Reserved
001
Reserved
010
2
011
3
100
Reserved
101
1.5
110
2.5
111
Reserved
BA0
MRS Type
0MRS
1EMRS
A12~A9
A8
A7
A6~A0
Operating Mode
0
Valid
Normal Operation
0
1
0
Valid
Normal Operation/ Reset DLL
00
1
VS
Vendor specific Test Mode
--
-
All other states reserved
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相關(guān)代理商/技術(shù)參數(shù) |
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| HY5DU12422BLTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
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| HY5DU12422BT-H-A | 制造商:Hynix Semi 功能描述: |
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