參數(shù)資料
型號(hào)： HW-V5-ML507-UNI-G-J
廠商： Xilinx Inc
文件頁(yè)數(shù)： 24/91頁(yè)
文件大?。?/td> 0K
描述： EVAL PLATFORM V5 FXT
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-5 FXT
類型： FPGA
適用于相關(guān)產(chǎn)品： ML507
所含物品： ML507 平臺(tái)，DVI 適配器，小型閃存卡和 SATA 轉(zhuǎn)接線
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
30
Switching Characteristics
All values represented in this data sheet are based on
speed specification version 1.62. Switching characteristics
are specified on a per-speed-grade basis and can be
designated as Advance, Preliminary, or Production. Each
designation is defined as follows:
Advance
These specifications are based on simulations only and are
typically available soon after device design specifications
are frozen. Although speed grades with this designation are
considered relatively stable and conservative, some under-
reporting might still occur.
Preliminary
These specifications are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production
These specifications are released once enough production
silicon of a particular device family member has been
characterized to provide full correlation between
specifications and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device.
Table 54 correlates the current status of each Virtex-5
device on a per speed grade basis.
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test
patterns. Listed below are representative values.
For more specific, more precise, and worst-case
guaranteed data, use the values reported by the static
timing analyzer and back-annotate to the simulation net list.
Unless otherwise noted, values apply to all Virtex-5 devices.
Table 54: Virtex-5 Device Speed Grade Designations
Device
Speed Grade Designations
Advance
Preliminary
Production
XC5VLX20T
-2, -1
XC5VLX30
-3, -2, -1
XC5VLX30T
-3, -2, -1
XC5VLX50
-3, -2, -1
XC5VLX50T
-3, -2, -1
XC5VLX85
-3, -2, -1
XC5VLX85T
-3, -2, -1
XC5VLX110
-3, -2, -1
XC5VLX110T
-3, -2, -1
XC5VLX155
-3, -2, -1
XC5VLX155T
-3, -2, -1
XC5VLX220
-2, -1
XC5VLX220T
-2, -1
XC5VLX330
-2, -1
XC5VLX330T
-2, -1
XC5VSX35T
-3, -2, -1
XC5VSX50T
-3, -2, -1
XC5VSX95T
-2, -1
XC5VSX240T
-2, -1
XC5VTX150T
-2, -1
XC5VTX240T
-2, -1
XC5VFX30T
-3, -2, -1
XC5VFX70T
-3, -2, -1
XC5VFX100T
-3, -2, -1
XC5VFX130T
-3, -2, -1
XC5VFX200T
-2, -1
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