Confidential
HV7131R
Pin Description
Pin
1
2
3
This document is a general product description and is subject to change without notice. MagnaChip
Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent
licenses are implied.
- 8 -
2004 MagnaChip Semiconductor Ltd.
Type
G
I
G
Symbol
DGNDI
SCK
DGNDI
Description
Ground for I/O Buffer.
I2C Clock Input.
Ground for I/O Buffer.
ENB signal enables Sensor : High(Sensor Enabled),
Low(Sensor Disabled, External Power Down)
Ground for I/O Buffer.
No Connection.
Master Input Clock.
Video Output Clock.
Ground for Analog Block.
Power for Analog Block.
No Connection.
Image Output Data Bit 9.
Image Output Data Bit 8.
Ground for I/O Buffer.
Image Output Data Bit 7.
Image Output Data Bit 6.
Image Output Data Bit 5.
Image Output Data Bit 4.
Ground for I/O Buffer.
Image Output Data Bit 3.
Image Output Data Bit 2.
No Connection.
Image Output Data Bit 1.
Image Output Data Bit 0.
Ground for I/O Buffer.
Ground for Internal Digital Block.
Power for Internal Digital Block.
Power for I/O Buffer.
Sensor Reset, Low Active.
No Connection.
Strobe Signal Output.
Video Frame Synchronization signal. / Frame Start output
VSYNC is active at start of image data frame.
Video Horizontal Line Synchronization signal. / Data is valid,
when HSYNC is High.
Ground for I/O Buffer.
I2C Standard data I/O port.
4
I
ENB
5
G
N
I
O
G
P
N
O
O
G
O
O
O
O
G
O
O
N
O
O
G
G
P
P
I
N
O
O
DGNDI
NC
MCLK
VCLK
AGND
AVDD
NC
DATA[9]
DATA[8]
DGNDI
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DGNDI
DATA[3]
DATA[2]
NC
DATA[1]
DATA[0]
DGNDI
DGNDC
DVDDC
DVDDI
RESETB
NC
STROBE
VSYNC
6~7
8
9
10~11
12~13
14~15
16
17
18
19
20
21
22
23
24
25
26~27
28
29
30
31
32
33
34
35
36
37
38
O
HSYNC
39
40
G
B
DGNDI
SDA