參數(shù)資料
型號: HV7131R
廠商: Electronic Theatre Controls, Inc.
元件分類: 圖像傳感器
英文描述: CMOS Image Sensor
中文描述: CMOS圖像傳感器
文件頁數(shù): 22/33頁
文件大?。?/td> 1481K
代理商: HV7131R
Confidential
HV7131R
1. VGA size when Programmable Window is disabled and ABLC enable
VGA Frame Timing Related Parameters
Master Clock Frequency(MCF)
25Mhz
Sensor Clock Frequency(SCF)
DCF/2 =12.5Mhz
HBLANK Value
VSYNC Mode
Line Mode
ABLC
Enable
If Integration Time < Core Frame Time, Real Frame Time is
2(208 + 640)SCPs + 4(208 + 512)SCPs + 480(208 + 640)SCPs + 8(208 + 640)SCPs
= 418400 SCPs =418400 X 80ns = 33.47msec = 29.87fps
else Real Frame Time is
Integration Time * SCPs + 8 * (208 +640) SCPs.
HOLD SLOT in frame timing appears only if integration time is larger then core frame time
This document is a general product description and is subject to change without notice. MagnaChip
Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent
licenses are implied.
- 22 -
2004 MagnaChip Semiconductor Ltd.
Clock Division
Sensor Clock Period(SCP)
VBLANK Value
Line Clock Period(LCP)
Programmable Window
MCF/1 = 25Mhz
1/12.5Mhz = 80ns
8
848 SCPs
OFF
208
2. VGA size when Programmable Window is disabled and ABLC disable
LCP(848SCPs)
IDLE SLOT(2LCP)
HOLD SLOT
Integration time – Core Frame Time
VBLANK[VSYNC] (8LCP)
HBLANK
(208 SCPs)
HSYNC(640 SCPs)
Active Data : 640 EA
Real Frame Time
Core Frame Time
480 LCPs
Video Height
4th
Line Data Flow
5th
Line Data Flow
HBLANK
(208 SCPs)
HSYNC(640 SCPs)
VCLK=12.5[Mhz]
LCP = 848 SCPs
482th
Line Data Flow
483th
Line Data Flow
Video Width(640SCP)
0~3
Line Data Flow for ABLC
ABLC Time
Hi - Z
Valid Data
DATA[9:0]
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