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參數(shù)資料
| 型號： | HPC46100 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | HPC46100 High-Performance microController with DSP Capability |
| 中文描述： | HPC46100高性能微控制器與DSP處理能力 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 436K |
| 代理商： | HPC46100 |
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IO Ports (Continued)
PORT I
Port I is an 8-bit input port that can be read as general
purpose inputs and can also be used for the following func-
tions
Pin
Alternate
Function
I0
R5B
Timer T5 R5B Input
I1
NMI
Nonmaskable Interrupt Input
I2
INT2
Maskable InterruptInput Capture
I3
INT3
Maskable InterruptInput Capture
I4
INT4
Maskable InterruptInput Capture
I5
SI
MICROWIREPLUS Data Input
I6
RDX
UART Data Input
I7
R6B
Timer T6 R6B Input and AD Trigger Input
PORT D
Port D is an 8-bit input port that can be used as general
purpose digital inputs and as analog inputs for the AD con-
verter
PORT P
Port P is a 3-bit inputoutput port that is used as general
purpose outputs or IO that is controlled by timers T4 T5
and T6 These pins can be configured as Pulse Width Modu-
lated Outputs (PWM) capture inputs or event counter in-
puts
POWER SUPPLY PINS
Four pairs of power supply pins are provided to minimize
cross talk between the analog digital and output driver sec-
tions of the chip
Pin
Function
VCC
Power for Digital Logic
GND
Ground for Digital Logic
DVCC
Power for Output Drivers
DGND
Ground for Output Drivers
AVCC
Power for Analog Logic
AVSS
Ground for Analog Logic
VREF
AD Converter Reference Voltage Input
AGND
Ground Reference for Analog Logic
CLOCK PINS
Pin
Function
CKI
System Oscillator InputExternal Clock Input
CKO
System Oscillator Output (Inversion of CKI)
CK2
Clock Output (CKI divided by 2)
OTHER PINS
Pin
Function
RESET
System reset input active low
PALE
Slow peripheral address latch enable
RDYHLD
Has two uses selected by a software bit
It’s either a READY input to extend the
bus cycle for slower memories or HOLD
request input to put the bus in a high
impedance state for DMA purposes
WO
This is an active low open drain output
that signals an illegal situation has been
detected by the WATCHDOG logic
ST1
Bus Cycle Status Output indicates first
opcode fetch
ST2
Bus Cycle Status Output indicates
machine states (skip interrupt and first
instruction cycle)
EXM
External memory enable (active high)
disables internal ROM and maps it to
external memory
EI
Has two uses it’s either an active low
level external interrupt with vector
address FFF3FFF2 which is shared with
the UART or Timer T4 R4B input
14
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