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參數(shù)資料
| 型號： | HPC46100 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | HPC46100 High-Performance microController with DSP Capability |
| 中文描述： | HPC46100高性能微控制器與DSP處理能力 |
| 文件頁數(shù)： | 29/32頁 |
| 文件大小： | 436K |
| 代理商： | HPC46100 |
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AD Converter Specifications
VCC e 5V g10% (VSS b 0050V) s Any Input s (VCC a 0050V) fIN e 24 MHz
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
Bits
Reference Voltage Input
AGND e 0V
3
VCC
V
Absolute Accuracy
VREF e VCC
g
1
LSB
Non-Linearity
VREF e VCC
Deviation from the
g
LSB
Best Straight Line
Differential Non-Linearity
VREF e VCC
g
LSB
Input Reference Resistance
16
48
kX
Common Mode Input Range (Note 6)
AGND
VREF
V
DC Common Mode Error
g
LSB
Off Channel Leakage Current
1
m
A
On Channel Leakage Current
1
m
A
AD Clock Frequency (Note 7)
01
20
MHz
Conversion Time (Note 8)
130
AD Clock
Cycle
Note 6
For VIN(b) t VIN(a) the digital output code will be 0000 0000 Two on-chip diodes are tied to each analog input The diodes will forward conduct for
analog input voltages below ground or above the VCC supply Be careful during testing at low VCC levels (45V) as high level analog inputs (5V) can cause this
input diode to conductespecially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode
This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 VDC
to5VDC input voltage range will therefore require a minimum supply voltage of 4950 VDC over temperature variations initial tolerance and loading
Note 7
See Prescaler description
Note 8
Conversion Time includes sample and hold time See following diagrams
TLDD11289 – 33
Note
The trigger condition generated by the start conversion method selected by the SC bits requires one CK2 to propagate through before the trigger condition is
known Once the trigger condition is known the sample and hold will start at the next rising edge of ADCLK The diagram shows worst case
6
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