參數(shù)資料
型號(hào)： HPC46100
廠商： National Semiconductor Corporation
英文描述： HPC46100 High-Performance microController with DSP Capability
中文描述： HPC46100高性能微控制器與DSP處理能力
文件頁(yè)數(shù)： 28/32頁(yè)
文件大?。?/td> 436K
代理商： HPC46100
40 MHz (Continued)
AC Electrical Characteristics (Continued)
See Notes 1 and 4 and
Figure 1 thru Figure 5 VCC e 50V g10% unless otherwise specified TA e 25 C one wait state
Symbol
Parameter
Min
Max
Units
E SIGNAL TIMING PARAMETERS
tRWSE e 025 tC b 7WR Falling Edge to E Rising Edge
55
ns
tRWHE e 05 tC b 7
E Falling Edge to WR Rising Edge
18
ns
tASE e tC b 20
Address Valid to E Rising Edge
30
ns
tRDE e WS b 20
E Falling Edge to Data Input Valid
30
ns
SLOW PERIPHERAL TIMING PARAMETERS
tPLL e tC b 5
PALE Pulse Width
45
ns
tPST e 075 tC b 10
Address Valid to PALE Falling Edge
275
ns
tPVL e 075 tC b 15
Address Hold from PALE Falling Edge
225
ns
tPVP e 075 tC b 10
PALE Falling Edge to RD or WR Falling Edge
275
ns
tPCSA e 025 tC b 125
Chip Select Setup to PALE Falling Edge
0
ns
tPAS e 15 tC b 20
Address Setup to RD or WR Falling Edge
55
ns
tPCSS e tC b 15
Chip Select Setup to RD or WR Falling Edge
35
ns
tPCSH e 05 tC b 15
Chip Select Hold from RD or WR Rising Edge
10
ns
tPACC e 5tC b 25
Address Valid to Input Data Valid
225
ns
tPRD e 35 tC b 25
RD Falling Edge to Data In Valid
150
ns
tPDR e tC (max)
Data Hold after RD Rising Edge
0
50
ns
tPRW e 35 tC b 15
RD Strobe Width
160
ns
tPSW e 30 tC b 20
Data Setup before WR Rising Edge
130
ns
tPHW e tC b 20
Data Hold after WR Rising Edge
30
ns
tPWW e 35 tC b 15
WR Strobe Width
160
ns
Note
CL e 40 pF
Note 1
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (tCKIR and tCKIL) on CKI input less than 25 ns
Note 2
Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3
tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle begin executed If HLD falling
edge occurs later tHAE as long as (3 tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait states and ready input
Note 4
WS (tWAIT) x (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency tC e 40 MHz with
one wait state programmed
Note 5
Due to testing limitationsactual limits will be better
5
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