
Timing Waveforms
(Continued)
TL/DD/10422–8
FIGURE 6. CPU and DMA Write Cycles
TL/DD/10422–9
FIGURE 7. CPU and DMA Read Cycles
TL/DD/10422–10
FIGURE 8. CPU Ready Mode with 1 Wait State and Ready Wait Extension
TL/DD/10422–11
FIGURE 9. DMA Ready Mode with 2 Wait States and Ready Wait Extension
6