參數(shù)資料
型號: HPC-DEV-ISE2
廠商: National Semiconductor Corporation
英文描述: High-Performance Communications MicroController
中文描述: 高性能通信微控制器
文件頁數(shù): 3/30頁
文件大小: 362K
代理商: HPC-DEV-ISE2
AC Electrical Characteristics
(see Notes 1 and 4 and Figures 1 thru 5), V
CC
e
5V
g
10%, T
A
e
0
§
C to
a
70
§
C for HPC46400E,
b
40
§
C to
a
85
§
C for
HPC36400E
Symbol and Formula
Parameter and Notes
Min
Max
Units
Note
f
C
t
C1
e
1/f
C
Operating Frequency
2
20
MHz
Operating Period
50
500
ns
t
CKIH
CKI Rise Time
22.5
ns
t
CKIL
t
C
e
2/f
C
t
WAIT
e
t
C
CKI Fall Time
22.5
ns
CPU or DMA Timing Cycle
100
ns
CPU or DMA Wait State Period
100
ns
t
DC1C2R
Delay of CK2 Rising Edge after
CKI Falling Edge
0
55
ns
(Note 2)
t
DC1C2F
Delay of CK2 Falling Edge after
CKI Falling Edge
0
55
ns
(Note 2)
f
U
e
f
C
/8
External UART Clock Input Frequency
2.5
MHz
f
MW
External MICROWIRE/PLUS
Clock Input Frequency
1.25
MHz
t
HCK
e
4t
C1
a
14
HDLC Clock Input Period
214
ns
f
XIN
e
f
C
/22
External Timer Input Frequency
0.91
kHz
t
XIN
e
t
C
Pulse Width for Timer Inputs
100
ns
t
UWS
MICROWIRE Setup Time D Master
100
20
ns
ns
D Slave
t
UWH
MICROWIRE Hold Time D Master
20
50
ns
ns
D Slave
t
UWV
MICROWIRE Output Valid Time D Master
50
150
ns
ns
D Slave
t
SALE
e
*/4
t
C
a
40
t
HWP
e
*/4
t
C
a
35
t
HAE
e
*/4
t
C
a
100
t
HAD
e
±/4
t
C
a
85
HLD Falling Edge before ALE Rising Edge
115
ns
HLD Pulse Width
110
ns
HLDA Falling Edge after HLD Falling Edge
175
ns
(Note 3)
HLDA Rising Edge after HLD Rising Edge
210
ns
t
BF
t
BE
e
t
C
b
66
Bus Float after HLDA Falling Edge
66
ns
Bus Enable after HLDA Rising Edge
34
ns
C
T
M
P
E
Note 1:
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO. Spec’d t
C1R
, t
C1F
,
and CKI duty cycle limits are not tested but are guaranteed functional by design. Keep in mind that when SLOW mode is selected, f
C
(Operating Frequency) will be
the external frequency divided by 4 and that value should be used in all formulas relating to the AC Characteristics.
Note 2:
Do not design with this parameter unless CKI is driven with an active signal and SLOW mode is not selected. When using a passive crystal circuit, its
stability is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3:
t
HAE
is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU or DMA cycle being executed. If HLD
falling edge occurs later, t
HAE
as long as (3 t
C
a
4 WS
a
72 t
C
a
100) may occur depending on the following CPU instruction or DMA cycle, its wait states and
ready input.
Note 4:
WS (t
WAIT
)
c
(number of preprogrammed wait states). Minimum and maximum values are calculated at maximum operating frequency, f
C
e
20 MHz, with
one wait state preprogrammed. These values are guaranteed with AC loading of 100 pF on Port A, 50 pF on CK2, 80 pF on other outputs, and DC loading of the
pin’s DC spec non CMOS I
OL
or I
OH
.
3
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