TL/DD10422
H
PRELIMINARY
November 1992
HPC36400E/HPC46400E
High-Performance Communications MicroController
General Description
The HPC46400E is an upgraded HPC16400. Features have
been added to support V.120, the 8-bit mode has been en-
hanced to support all instructions, and the UART has been
changed to provide more flexibility and power. The
HPC46400E is fully upward compatible with the HPC16400.
The HPC46400E has 4 functional blocks to support a wide
range of communication application-2 HDLC channels, 4
channel DMA controller to facilitate data flow for the HDLC
channels, programmable serial interface and UART.
The serial interface decoder allows the 2 HDLC channels to
be used with devices using interchip serial link for point-to-
point and multipoint data exchanges. The decoder gener-
ates enable signals for the HDLC channels allowing multi-
plexed D and B channel data to be accessed.
The HDLC channels manage the link by providing sequenc-
ing using the HDLC framing along with error control based
upon a cyclic redundancy check (CRC). Multiple address
recognition modes, and both bit and byte modes of opera-
tion are supported.
The HPC36400E and HPC46400E are available in 68-pin
PLCC and 80-pin PQFP packages.
Features
Y
HPC
TM
familyDcore features:
D 16-bit data bus, ALU, and registers
D 64 kbytes of external memory addressing
D FAST!D20.0 MHz system clock
D Four 16-bit timer/counters with WATCHDOG
TM
logic
D MICROWIRE/PLUS
TM
serial I/O interface
D CMOSDlow power with two power save modes
Y
Two full duplex HDLC channels
D Optimized for ISDN, X.25, V.120, and LAPD
applications
D Programmable frame address recognition
D Up to 4.65 Mbps serial data rate
D Built in diagnostics
D Synchronous bypass mode
D Optional CRC generation
D Received CRC bytes can be read by the CPU
Y
Four channel DMA controller
Y
8- or 16-bit external data bus
Y
UART
D Full duplex
D 7, 8, or 9 data bits
D Even, odd, mark, space or no parity
D 7/8, 1 or 2 stop bit generation
D Accurate internal baud rate generation up to 625k
baud without penalty of using expensive crystal
D Synchronous and asynchronous modes of operation
Y
Serial Decoder
D Supports 6 popular time division multiplexing proto-
cols for inter-chip communications
D Optional rate adaptation of 64 kbit/s data rate to
56 kbit/s
Y
Over
(/2
Mbyte of extended addressing
Y
Easy interface to National’s DASL, ‘U’ and ‘S’ trans-
ceiversDTP3400, TP3410 and TP3420
Y
Commercial (0
§
C to
a
70
§
C) and industrial (
b
40
§
C to
a
85
§
C)
Block Diagram
TL/DD/10422–1
TapePak
é
and TRI-STATE
é
are registered trademarks of National Semiconductor Corporation.
HPC
TM
, MICROWIRE/PLUS
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation.
IBM
é
, PC-AT
é
are registered trademarks of International Business Machines Corporation.
Sun
é
is a registered trademark of Sun Microsystems.
SunOS
TM
is a trademark of Sun Microsystems.
UNIX
é
is a registered trademark of AT&T Bell Laboratories.
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
