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    參數(shù)資料
    型號(hào): HPC-DEV-ISE2
    廠商: National Semiconductor Corporation
    英文描述: High-Performance Communications MicroController
    中文描述: 高性能通信微控制器
    文件頁(yè)數(shù): 21/30頁(yè)
    文件大?。?/td> 362K
    代理商: HPC-DEV-ISE2
    Memory
    The HPC46400E has been designed to offer flexibility in
    memory usage. A total address space of 64 kbytes can be
    addressed with 256 bytes of RAM available on the chip it-
    self.
    Program memory addressing is accomplished by the 16-bit
    program counter on a byte basis. Memory can be addressed
    directly by instructions or indirectly through the B, X and SP
    registers. Memory can be addressed as words or bytes.
    Words are always accessed on even-byte boundaries. The
    HPC46400E uses memory-mapped organization to support
    registers, I/O and on-chip peripheral functions.
    The HPC46400E memory address space extends to 64
    kbytes and registers and I/O are mapped as shown in Table
    II.
    Extended Memory Addressing
    If more than 64k of addressing is desired in a HPC46400E
    system, on board bank select circuitry is available that al-
    lows four I/O lines of Port B (B8, B9, B13, B14) to be used
    in extending the address range. This gives the user a main
    routine area of 32k and 16 banks of 32k each for subroutine
    and data, thus getting a total of 536.5k of memory.
    Note:
    If all four lines are not needed for memory expansion, the unused
    lines can be used as general purpose inputs.
    The Extended Memory Addressing mode is entered by set-
    ting the EMA control bit in the Message Control Register. If
    this bit is not set, the port B lines (B8, B9, B13, B14) are
    available as general purpose I/O or synchronous outputs as
    selected by the BFUN register.
    The main memory area contains the interrupt vectors &
    service routines, stack memory, and common memory for
    the bank subroutines to use. The 16 banks of memory can
    contain program or data memory (note: since the on chip
    resources are mapped into addresses 0000-01FF, the first
    512 bytes of each bank are not usable, actual available
    memory is 536.5k).
    TABLE II. Memory Map
    FFFF–FFF0
    FFEF–FFD0
    Interrupt Vectors
    JSRP Vectors
    FFCF–FFCE
    :
    0201–0200
    :
    External Expansion
    USER MEMORY
    01FF–01FE
    :
    01C1–01C0
    :
    On Chip RAM
    USER RAM
    01BC
    01BA
    01B8
    01B6
    01B4
    01B2
    01B0
    CRC Byte 2
    CRC Byte 1
    Error Status
    Receiver Status
    Cntrl
    Recr Addr Comp Reg 2
    Recr Addr Comp Reg 1
    HDLC
    Y
    2
    01AC
    01AA
    01A8
    01A6
    01A4
    01A2
    01A0
    CRC Byte 2
    CRC Byte 1
    Error Status
    Receiver Status
    Cntrl
    Recr Addr Comp Reg 2
    Recr Addr Comp Reg 1
    HDLC
    Y
    1
    0195–0194
    WATCHDOG Register
    WATCHDOG Logic
    0193–0192
    0191–0190
    018F–018E
    018D–018C
    018B–018A
    0189–0188
    0187–0186
    0185–0184
    0183–0182
    0181–0180
    T0CON Register
    TMMODE Register
    DIVBY Register
    T3 Timer
    R3 Register
    T2 Timer
    R2 Register
    I2CR Register/ R1
    I3CR Register/ T1
    I4CR Register
    Timer Block T0–T3
    017F–017E
    017D–017C
    Baud Counter
    Baud Register
    UART Timer
    0179–0178
    0177–0176
    0175–0174
    0173–0172
    0171–0170
    Byte Count 2
    Field Addr 2
    Byte Count 1
    Field Addr 1
    Xmit Cntrl & Status
    DMAT
    Y
    2 (Xmit)
    016B–016A
    0169–0168
    0167–0166
    0165–0164
    0163–0162
    0161–0160
    Frame Length
    Data Addr 2
    Cntrl Addr 2
    Data Addr 1
    Cntrl Addr 1
    Recv Cntrl & Status
    DMAR
    Y
    2 (Recv)
    0159–0158
    0157–0156
    0155–0154
    0153–0152
    0151–0150
    Y
    Bytes 2
    Field Addr 2
    Y
    Bytes 1
    Field Addr 1
    Xmit Cntrl & Status
    DMAT
    Y
    1 (Xmit)
    014B–014A
    0149–0148
    0147–0146
    0145–0144
    0143–0142
    0141–0140
    Frame Length
    Data Addr 2
    Cntrl Addr 2
    Data Addr 1
    Cntrl Addr 1
    Recv Cntrl & Status
    DMAR
    Y
    1 (Recv)
    012C
    012A
    0128
    0126
    0124
    0122
    0120
    Baud
    PSR - Prescaler
    ENUR Register
    TBUF Register
    RBUF Register
    ENUI Register
    ENU Register
    UART
    0110
    010E
    010C
    010A
    0108
    0106
    FEXT Register
    Port R Pins
    DIR R Register
    Port R Data Register
    Message System Configuration
    Serial Decoder/Enable
    Configuration Reg
    Message Pending
    Message System Control
    Port D Input
    PORTS R & D
    0104
    0102
    0100
    00F5–00F4
    00F3–00F2
    00E6
    00E3–00E2
    BFUN Register
    DIR B Register
    Chip Revision Register
    Port B
    PORT B
    00DD–00DC
    00D8
    00D6
    00D4
    00D2
    00D0
    Halt Enable Register
    Port I Input Register
    SIO Register
    IRCD Register
    IRPD Register
    ENIR Register
    PORT CONTROL
    & INTERRUPT
    CONTROL
    REGISTERS
    00CF–00CE
    00CD–00CC
    00CB–00CA
    00C9–00C8
    00C7–00C6
    00C5–00C4
    00C3–00C2
    00C0
    X Register
    B Register
    K Register
    A Register
    PC Register
    SP Register
    (Reserved)
    PSW Register
    HPC CORE
    REGISTERS
    00BF–00BE
    :
    0001–0000
    On Chip
    RAM
    :
    USER RAM
    Note:
    All unused addresses are reserved by National Semiconductor
    21
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