參數(shù)資料
型號(hào)： HPC-DEV-ISE2
廠商： National Semiconductor Corporation
英文描述： High-Performance Communications MicroController
中文描述： 高性能通信微控制器
文件頁(yè)數(shù)： 12/30頁(yè)
文件大?。?/td> 362K
代理商： HPC-DEV-ISE2
Connection Diagrams
(Continued)
TL/DD/10422–32
Top View
See NS Package Number VHG80A
Wait States
The HPC46400E provides software selectable Wait States
for access to slower memories and for shared bus applica-
tions. The number of Wait States for the CPU are selected
by two bits in the PSW register. The number of Wait States
for DMA are selected by a bit in the Message System Con-
figuration register. Additionally, the RDY input may be used
to extend the RD or WR cycle, allowing the HPC to be used
in shared memory applications and allowing the user to in-
terface with slow memories and peripherals.
Power Save Modes
Two power saving modes are available on the HPC46400E:
HALT and IDLE. In the HALT mode, all processor activities
are stopped. In the IDLE mode, the on-board oscillator and
timer T0 are active but all other processor activities are
stopped. In either mode, on-board RAM, registers and I/O
are unaffected (except the HDLC and UART which are re-
set).
HALT MODE
The HPC46400E is placed in the HALT mode under soft-
ware control by setting bits in the PSW. All processor activi-
ties, including the clock and timers, are stopped. In the
HALT mode, power requirements for the HPC46400E are
minimal and the applied voltage (V
CC
) may be decreased
without altering the state of the machine. There are two
ways of exiting the HALT mode: via the RESET or the NMI.
The RESET input reinitializes the processor. Use of the NMI
input will generate a vectored interrupt and resume opera-
tion from that point with no initialization. The HALT mode
can be enabled or disabled by means of a control register
HALT enable. To prevent accidental use of the HALT mode
the HALT enable register can be modified only once.
IDLE MODE
The HPC46400E is placed in the IDLE mode through the
PSW. In this mode, all processor activity, except the on-
board oscillator and Timer T0, is stopped. The HPC46400E
resumes normal operation upon timer T0 overflow. As with
the HALT mode, the processor is also returned to full opera-
tion by the RESET or NMI inputs, but without waiting for
oscillator stabilization.
SLOW MODE
The HPC46400E is placed in the SLOW mode under soft-
ware control by setting ‘‘SLOW’’ bit in ‘‘FEXT’’ Feature Ex-
tension register. In this mode CKI is divided by 4 and each
CK2 cycle will be 8 CKI clock cycles. This reduction in fre-
quency of operation of HPC16400E is achieved without al-
tering the state of the machine. CKI and CKO signals remain
unaffected reagardless of the status of the SLOW bit. At
RESET the ‘‘SLOW’’ bit comes up as 0, i.e., the clocking of
the HPC46400E is normal. Software can cause the division
to be enabled or disabled by writing a 1 or a 0 to the
‘‘SLOW’’ bit. Note that when the ‘‘SLOW’’ bit is set to 1,
HALT or IDLE power down mode cannot be entered,
‘‘SLOW’’ bit has to be cleared to a 0 first.
12
相關(guān)PDF資料
PDF描述
HPC-DEV-ISE2-E High-Performance Communications MicroController
HPC-DEV-SYS2-E CABLE, COAX, RG179, BROWN, 3MM, 25M; Length, Reel (Imperial):82ft; Attenuation, 400MHz:68.90dB; Capacitance:75pF/m; Conductor make-up:7/0.102 mm; Diameter, External:3.00mm; Impedance:75R; Length, Reel (Metric):25m; Resistance, per RoHS Compliant: Yes
HPC-DEV-SYS2 High-Performance Communications MicroController
HPC-DEV-WDBC High-Performance microController with A/D
HPC46004VF20 High-Performance microController with A/D
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HPC-DEV-ISE2-E 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController
HPC-DEV-ISE4 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance microController with A/D
HPC-DEV-ISE-E 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance microController with A/D
HPC-DEV-SUNC 制造商:Rochester Electronics LLC 功能描述:- Bulk
HPC-DEV-SUNDB 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController
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