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參數(shù)資料
| 型號： | HMS81C4316 |
| 英文描述： | [TV : OSD/ I?C] |
| 中文描述： | [電視：OSD /我？?] |
| 文件頁數(shù)： | 58/94頁 |
| 文件大?。?/td> | 1652K |
| 代理商： | HMS81C4316 |
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HMS81032E/HMS81032TL
54
Nov. 2001 Ver 2.00
15. STANDBY FUNCTION
15.1 Sleep Mode
SLEEP mode can be entered by setting the bit of SLEEP
mode register (SLPM). In the mode, CPU clock stops but
oscillator keeps running. B.I.T and a part of peripheral
hardware execute, but prescaler output which provide
clock to peripherals can be stopped by program. (Except,
PS10 can’t stopped.) In SLEEP mode, more consuming
power can be saved by not using other peripheral hardware
except for B.I.T. By setting ENPCK (peripheral clock con-
trol bit) of CKCTLR (clock control register) to “0”, periph-
eral hardware halted, and SLEEP mode is entered. To
release SLEEP mode by BITR (basic interval timer inter-
rupt), bit10 of prescaler should be selected as B.I.T input
clock before entering SLEEP mode. “NOP” instruction
should be follows setting of SLEEP mode for rising pre-
charge time of data bus line.
(ex) setting of SLEEP mode : set the bit of SLEEP
; mode register (SLPM)
NOP : NOP instruction
15.2 Stop Mode
STOP mode can be entered by STOP instruction during
program. In STOP mode, oscillator is stopped to make all
clocks stop, which leads to less power consumption. All
registers and RAM data are preserved. “NOP” instruction
should be follows STOP instruction for rising precharge
time of Data Bus line.
(ex) STOP : STOP instruction execution
NOP : NOP instruction
Sleep Mode Control Register (W)
SLPM
ADDRESS: 0F0
INITIAL VALUE: -------0b
-
SLPM0
0: Sleep mode release
1: sleep mode
Clock Control Register (W)
CKCTLR
ADDRESS: 0C7
INITIAL VALUE: --110111b
0
1
2
3
4
5
6
7
ENPCK 0: Stopped
1: Provided
-
-
-
-
-
-
0
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