參數(shù)資料
型號(hào)： HMS81C4316
英文描述： [TV : OSD/ I?C]
中文描述： [電視：OSD /我？?]
文件頁數(shù)： 51/94頁
文件大?。?/td> 1652K
代理商： HMS81C4316
HMS8132E/HMS81032TL
Nov. 2001 Ver 2.00
47
14.1 Interrupt priority and sources
Each interrupt vector is independent and has its own pri-
ority. Software interrupt (BRK) is also available. Interrupt
source classification is shown in Table 14-1.
14.2 Interrupt control register
I flag of PSW is a interrupt mask enable flag. When I flag
= “0”, all interrupts become disable. When I flag = “1”, in-
terrupts can be selectively enabled and disabled by con-
tents of corresponding Interrupt Enable Register. When
interrupt is occurred, interrupt request flag is set, and Inter-
rupt request is detected at the edge of interrupt signal. The
accepted interrupt request flag is automatically cleared
during interrupt cycle process. The interrupt request flag
maintains “1” until the interrupt is accepted or is cleared in
program. In reset state, interrupt request flag register
(IRQH, IRQL) is cleared to “0”. It is possible to read the
state of interrupt register and to manipulate the contents of
register and to generate interrupt. (Refer to software inter-
rupt)
Mask
Priority
Reset/Interrupt
Symbol
INT Vector H
INT Vector L
Hardware Interrupt
Non-maskable
-
Hardware Reset
RESET
FFFF
FFFE
maskable
1
Key Scan
KSCNR
FFFB
FFFA
2
External Interrupt1
INT1R
FFF9
FFF8
3
External Interrupt2
INT2R
FFF7
FFF6
4
Timer0
T0R
FFF3
FFF2
5
Timer1
T1R
FFF1
FFF0
6
Timer2
T2R
FFEF
FFEE
7
Watch Dog Timer
WDTR
FFE9
FFE8
8
Basic Interval Timer
BITR
FFE7
FFE6
Software Interrupt
-
-
BRK Instruction
BRK
FFDF
FFDE
Table 14-1 Interrupt Source
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