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參數(shù)資料
| 型號： | HMS81C4316 |
| 英文描述： | [TV : OSD/ I?C] |
| 中文描述： | [電視：OSD /我？?] |
| 文件頁數(shù)： | 53/94頁 |
| 文件大?。?/td> | 1652K |
| 代理商： | HMS81C4316 |
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HMS8132E/HMS81032TL
Nov. 2001 Ver 2.00
49
14.4 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the
interrupt latch is cleared to “0” by a reset or an instruction. Inter-
rupt acceptance sequence requires 8
f
XIN
after the completion of
the current instruction execution. The interrupt service task is ter-
minated upon execution of an interrupt return instruction [RETI].
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
5. The instruction stored at the entry address of the inter-
rupt service program is executed.
l
Figure 14-3 Interrupt Accept Mode & Selection by IP3~IP0
BTCL
IP3
7
6
5
4
3
2
1
0
IM1
INITIAL VALUE: --000000
B
ADDRESS: 0CA
H
IMOD
IP1
IP0
R/W
R/W
R/W
R/W
R/W
R/W
IM0
Interrupt mode register
Selection interrupt
0001: KSCNR
0010: INT1R
0011: INT2R
0101: T0R
0110: T1R
0111: T2R
1010: WDTR
1011: BITR
00: Fixed by hardware
01: Changeable by IP3~IP0
1x: Interrupt is inhibited
Priority
R/W
R/W
-
-
IP2
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