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參數資料
| 型號： | HMPVIDEVALISA |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數： | 36/43頁 |
| 文件大?。?/td> | 183K |
| 代理商： | HMPVIDEVALISA |
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36
Pin Description
PIN
NAME
PIN
NUMBER
INPUT/
OUTPUT
DESCRIPTION
P0-P15
42, 43, 45,
47-51, 54-58,
60, 63, 64
O
Pixel output pins. See Table 3.
HSYNC
71
O
Horizontal sync output. HSYNC is asserted during the horizontal sync intervals. The
polarity of HSYNC is programmable. This pin is three-stated after a RESET or soft-
ware reset and should be pulled high through a 10K resistor.
VSYNC
70
O
Vertical sync output. VSYNC is asserted during the vertical sync intervals. The polar-
ity of VSYNC is programmable. This pin is three-stated after a RESET or software re-
set and should be pulled high through a 10K resistor.
FIELD
67
O
FIELD output. The polarity of FIELD is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10K resistor.
BLANK
65
O
Composite blanking output. BLANK is asserted during the horizontal and vertical
blanking intervals. The polarity of is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10K resistor.
DVALID
66
O
Data valid output. DVALID is asserted during CLK2 cycles that contain valid pixel da-
ta. This pin is three-stated after a RESET or software reset and should be pulled high
through a 10K resistor.
CLK2
38, 13
I
2x pixel clock inputs. All CLK2 pins must be connected together. This clock must be
a continuous, free-running clock.
RESET
34
I
Reset control input. A logical zero for a minimum of four CLK2 cycles resets the de-
vice. RESET must be a logical one for normal operation.
SDA
40
I/O
I
2
C interface data input/output.
SCL
41
I
I
2
C interface clock input.
WPE
27
I
White Peak Enable. When enabled (“1”), the video gain is reduced when the A/D out-
put code exceeds 248. When disabled (“0”), the video amplifier will clip when the A/D
output code reaches code 255.
VBIVALID
61
O
Vertical Blanking Interval Valid output. VBIVALID is asserted during CLK2 cycles that
contain valid VBI (Vertical Blanking Interval) data such as Closed Captioning, Tele-
text, and Wide Screen Signalling data. The polarity of VBIVALID is programmable.
This pin is three-stated after a RESET or software reset and should be pulled high
through a 10K resistor.
INTREQ
44
O
Interrupt Request Output. This is an open-drain output and requires an external 10K
pull-up resistor to V
CC
.
NTSC/PAL 1
7
I
Composite Video Input. This input must be AC-coupled to the video signal (using a
1
μ
F capacitor) and terminated with a 75
resistor, as shown in the Applications sec-
tion. These components should be as close to this pin as possible for best perfor-
mance. If not used, this pin should be connected to AGND through a 0.1
μ
F capacitor.
NTSC/PAL 2
6
I
Composite Video Input. This input must be AC-coupled to the video signal (using a
1
μ
F capacitor) and terminated with a 75
resistor, as shown in the Applications sec-
tion. These components should be as close to this pin as possible for best perfor-
mance. If not used, this pin should be connected to AGND through a 0.1
μ
F capacitor.
NTSC/PAL 3
(Y)
5
I
Composite video or Luminance (Y) video input. This input must be AC-coupled to the
video signal (using a 1
μ
F capacitor) and terminated with a 75
resistor, as shown in
the Applications section. These components should be as close to this pin as possi-
ble for best performance. If not used, this pin should be connected to AGND through
a 0.1
μ
F capacitor.
HMP8115
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| HMPW-KI-M/N | 制造商:Newport Electronics Inc 功能描述:IEC MINI HITEMP WIN CONN GREEN |
| HMPW-K-M/N | 制造商:Newport Electronics Inc 功能描述:MINIATURE CONNECTOR 制造商:Newport Electronics Inc 功能描述:MINIATURE CONNECTOR, For Use With:K Type Thermocouple, Accessory Type:Temperatur |
| HM-PWR-HDR-01-LR | 功能描述:硬公制連接器 HMPWR RAHDR 10.9, 10.9,10.9 PDNIG,ROHS RoHS:否 制造商:TE Connectivity / AMP 系列:Z-Pack 產品類型:Receptacles 排數:5 位置/觸點數量:110 安裝角:Right 端接類型:Pin 外殼材料:Polyester 觸點材料:Phosphor Bronze 觸點電鍍:Gold 類型: |
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