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參數(shù)資料
| 型號： | HMPVIDEVALISA |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 25/43頁 |
| 文件大小： | 183K |
| 代理商： | HMPVIDEVALISA |
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TABLE 14. GENLOCK CONTROL REGISTER
SUB ADDRESS = 04
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Aspect Ratio
Mode
0 = Rectangular (BT.601) pixels
1 = Square pixels
0
B
6
Freeze Output
Timing Enable
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit
to a “0” resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
0
B
5
DVALID Duty Cycle
Control
(DVLD_DCYC)
This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID has 50/50 duty cycle at the pixel output datarate
1 = DVALID goes active based on linelock. This will cause DVALID to not have a 50/50
duty cycle. This bit is intended to be used in maintaining backward compatibilty with the
HMP8112A DVALID output timing.
0
B
4
DVALID Line Tim-
ing Control
(DVLD_LTC)
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID present only during active video time on active scan lines
1 = DVALID present the entire scan line time on all scan lines
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output sig-
nal as:
0 = Normal timing
1 = DVALID signal ANDed with CLK2
0
B
3
Missing HSYNC
Detect Select
This bit specifies the number of missing horizontal sync pulses before the device goes
into the horizontal lock acquisition mode. In mode “0”, the default value of the HPLL Ad-
just register should be used. In mode “1”, the typical values the HPLL Adjust register
should be 10
H
to 20
H
.
0 = 12 pulses
1 = 1 pulse
0
B
2
Missing VSYNC
Detect Select
This bit specifies the number of missing vertical sync pulses before the device goes into
the vertical lock acquisition mode.
0 = 3 pulses
1 = 1 pulse
0
B
1-0
CLK2 Frequency
This bit indicates the frequency of the CLK2 input clock.
00 = 24.54MHz
01 = 27.0MHz
10 = 29.5MHz
11 = Reserved
01
B
TABLE 15. ANALOG INPUT CONTROL REGISTER
SUB ADDRESS = 05
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-3
Reserved
00000
B
2-0
Video Signal
Input Select
000 = NTSC/PAL 1
001 = NTSC/PAL 2
010 = NTSC/PAL 3
011 = S-video
100 = reserved
101 = reserved
110 = reserved
111 = reserved
000
B
HMP8115
相關PDF資料 |
PDF描述 |
|---|---|
| HMP8115 | NTSC/PAL Video Decoder |
| HMP8115CN | NTSC/PAL Video Decoder |
| HMR100 | Hadware Manual |
| HMR-100 | Hadware Manual |
| HMS188CWHRLP-20 | x8 SRAM |
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