參數(shù)資料
型號(hào)： HMPVIDEVALISA
廠商： Intersil Corporation
英文描述： NTSC/PAL Video Decoder
中文描述： NTSC / PAL視頻解碼器
文件頁數(shù)： 29/43頁
文件大小： 183K
代理商： HMPVIDEVALISA
29
TABLE 22. INTERRUPT MASK REGISTER
SUB ADDRESS = 0F
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Genlock Loss
Interrupt Mask
If this bit is a “1”, an interrupt is generated when genlock is lost.
0 = Interrupt disabled
1 = Interrupt enabled
0
B
6
Input Signal Loss
Interrupt Mask
If this bit is a “1”, an interrupt is generated when a video signal is no longer detected on
the selected video input.
0 = Interrupt disabled
1 = Interrupt enabled
0
B
5
Closed Caption
Interrupt Mask
If this bit is a “1”, an interrupt is generated when the Caption_ODD_A and
Caption_ODD_B or the Caption_EVEN_A and Caption_EVEN_B data registers contain
new data.
0 = Interrupt disabled
1 = Interrupt enabled
0
B
4
WSS
Interrupt Mask
If this bit is a “1”, an interrupt is generated when the WSS_ODD_A and WSS_ODD_B or
the WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
0 = Interrupt disabled
1 = Interrupt enabled
0
B
3
Teletext
Interrupt Mask
If this bit is a “1”, an interrupt is generated when teletext information is first detected at
the beginning of each field.
0 = Interrupt disabled
1 = Interrupt enabled
0
B
2-1
Reserved
00
B
0
Vertical Sync
Interrupt Mask
If this bit is a “1”, an interrupt is generated at the beginning of each field.
0 = Interrupt disabled
1 = Interrupt enabled
0
B
TABLE 23. INTERRUPT STATUS REGISTER
SUB ADDRESS = 10
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Genlock Loss
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that genlock was lost. To clear
the interrupt request, a “1” must be written to this bit.
0
B
6
Input Signal Loss
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that the input video source is
no longer present. To clear the interrupt request, a “1” must be written to this bit.
0
B
5
Closed Caption
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that the Caption_ODD_A and
Caption_ODD_B or the Caption_EVEN_A and Caption_EVEN_B data registers contain
new data. To clear the interrupt request, a “1” must be written to this bit.
0
B
4
WSS
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that the WSS_ODD_A and
WSS_ODD_B or the WSS_EVEN_A and WSS_EVEN_B data registers contain new da-
ta. To clear the interrupt request, a “1” must be written to this bit.
0
B
3
Teletext
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that teletext data has been de-
tected in the current field. To clear the interrupt request, a “1” must be written to this bit.
0
B
2-1
Reserved
00
B
0
Vertical Sync
Interrupt Status
If this bit is a “1”, the reason for the interrupt request was that a new field was started. To
clear the interrupt request, a “1” must be written to this bit.
0
B
HMP8115
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