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參數(shù)資料
| 型號： | HMPVIDEVALISA |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數(shù)： | 14/43頁 |
| 文件大?。?/td> | 183K |
| 代理商： | HMPVIDEVALISA |
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14
8-BIT BT.656 OUTPUT
If BT.656 data is generated, it is output following each rising
edge of CLK2. The BT.656 EAV and SAV formats are shown
in Table 4 and the pixel output timing is shown in Figure 16.
The EAV and SAV timing is determined by the programmed
horizontal and vertical blank timing
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2.
For proper operation, CLK2 must be exactly 2x the desired
output sample rate. The DVALID output is continuously
asserted during the entire active video time.
During the blanking intervals, the YCbCr outputs have a
value of 16 for Y and 128 for Cb and Cr, unless ancillary data
is present.
Due to the use of digital PLLs and source video timing the
total # of samples per line may not equal exactly 1716
(NTSC) or 1728 (PAL). The active video portion of the
BT.656 data stream is always exactly 1440 continuous sam-
ples. Any line-to-line timing difference from nominal # of
samples per line, plus or minus, is accommodated in the hor-
izontal blanking interval.
NOTES:
14. Y
0
is the first active luminance pixel of a line. Cb
0
and Cr
0
are first active chrominance pixels in a line. Cb and Cr will alternate every
cycle due to the 4:2:2 subsampling.
15. BLANK is asserted per Figure 9.
16. DVALID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output and
will appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
FIGURE 14. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
Y
0
Cb
0
Y
1
Cr
0
Y
2
Cb
2
Y
3
Cr
2
Y
4
Cb
4
CLK
DVALID
P15-P8
P7-P0
t
DVLD
NOTES:
17. BLANK is asserted per Figure 9.
18. DAVLID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output
and will appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
FIGURE 15. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
R0
G
0
R
1
G
0
R
2
G
2
R
3
G
2
R
4
G
4
CLK
DVALID
BLANK
t
DVLD
B
0
B
1
B
2
B
3
B
4
P15-P11
[P14-P10]
P10-P5
[P9-P5]
P4-P0
HMP8115
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