
HM514265D Series, HM51S4265D Series
7
DC Characteristics
(Ta = 0 to 70
°C, V
CC = 5 V ±5%, VSS = 0 V) (HM51(S)4265D-5/6R) *
5
(Ta = 0 to +70
°C, V
CC = 5 V ±10%, VSS = 0 V)(HM51(S)4265D-6/7/8) *
5
HM514265D, HM51S4265D
-5
-6/6R
-7
-8
Parameter
Symbol Min
Max Min
Max Unit Test conditions
Operating
current*
1, *2
I
CC1
—
160
—
150
—
140
—
125
mA
RAS, UCAS, LCAS
cycling, t
RC = min
Standby current
I
CC2
—
2
—
2
—
2
—
2
mA
TTL interface
RAS, UCAS, LCAS = V
IH
Dout = High-Z
—
1
—
1
—
1
—
1
mA
CMOS interface
RAS, UCAS, LCAS, WE,
OE
≥ V
CC – 0.2 V
Dout = High-Z
Standby current
(L-version)
I
CC2
—
200
—
200
—
200
—
200
A CMOS interface
RAS, UCAS, LCAS, WE,
OE
≥ V
CC – 0.2 V
Dout = High-Z
RAS-only refresh
current*
2
I
CC3
—
150
—
140
—
130
—
110
mA
t
RC = min
CAS-before-RAS
refresh current*
2
I
CC6
—
150
—
140
—
130
—
110
mA
t
RC = min
EDO page mode
current*
1, *3
I
CC4
—
180
—
180
—
150
—
130
mA
t
HPC = min
Battery backup
current*
4
(Standby with CBR
refresh) (L-version)
I
CC10
—
300
—
300
—
300
—
300
A Standby: CMOS interface
Dout = High-Z
CBR refresh: t
RC = 250 s
t
RAS ≤ 1 s,
UCAS, LCAS = V
IL
WE, OE = V
IH
Self-refresh mode
current
(HM51S4265D)
I
CC11
—
1
—
1
—
1
—
1
mA
CMOS interface,
RAS,
UCAS, LCAS
≤ 0.2 V,
Dout = High-Z
Self-refresh mode
current
(HM51S4265DL)
I
CC11
—
200
—
200
—
200
—
200
A CMOS interface, RAS,
UCAS, LCAS
≤ 0.2 V,
Dout = High-Z
Input leakage
current
I
LI
–10
10
–10
10
–10
10
–10
10
A 0 V ≤ Vin ≤ 6.5 V
Output leakage
current
I
LO
–10
10
–10
10
–10
10
–10
10
A 0 V ≤ Vout ≤ 6.5 V
Dout = disable
Output high voltage V
OH
2.4
V
CC
2.4
V
CC
2.4
V
CC
2.4
V
CC
V
High Iout = –2 mA
Output low voltage
V
OL
0
0.4
0
0.4
0
0.4
0
0.4
V
Low Iout = 2 mA
Notes: 1. I
CC depends on output load condition when the device is selected.
I
CC max is specified at the
output open condition.
2. Address can be changed twice or less while
RAS = V
IL.