72
7. Wakeup Edge Select Register (WEGR)
Bit
Initial value
Read/Write
7
WKEGS7
0
R/W
6
WKEGS6
0
R/W
5
WKEGS5
0
R/W
4
WKEGS4
0
R/W
3
WKEGS3
0
R/W
0
WKEGS0
0
R/W
2
WKEGS2
0
R/W
1
WKEGS1
0
R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.
WEGR is initialized to H'00 by a reset.
Bit n:
WKP
n edge select (WKEGSn)
Bit n selects
WKP
n pin input sensing.
Bit n
WKEGS
Description
WKP
n pin falling edge detected
WKP
n pin rising edge detected
0
(initial value)
1
(n = 7 to 0)
3.3.3
External Interrupts
There are 12 external interrupts: IRQ
4
to IRQ
0
and WKP
7
to WKP
0
.
1. Interrupts WKP
7
to WKP
0
Interrupts WKP
7
to WKP
0
are requested by either rising or falling edge input to pins
WKP
7
to
WKP
0
. When these pins are designated as pins
WKP
7
to
WKP
0
in port mode register 5 and a
rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP
7
to WKP
0
interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 9 is assigned to interrupts WKP
7
to WKP
0
. All eight interrupt sources have the same
vector number, so the interrupt-handling routine must discriminate the interrupt source.
2. Interrupts IRQ
4
to IRQ
1
Interrupts IRQ4 to IRQ
1
are requested by input signals to pins
IRQ
4
to
IRQ
1
. These interrupts are
detected by either rising edge sensing or falling edge sensing, depending on the settings of bits
IEG
4
to IEG
1
in IEGR.