參數(shù)資料
型號(hào)： HD404849FS
廠商： Hitachi,Ltd.
元件分類： 其它接口
英文描述： TERMINAL
中文描述： IGBT模塊
文件頁數(shù)： 9/125頁
文件大?。?/td> 471K
代理商： HD404849FS
HD404849 Series
9
Interrupt control bits area
63
55
54
51
50
49
48
46
45
44
41
40
39
38
37
36
35
32
31
28
27
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
0
V register
Port R7 DCR
Port R6 DCR
Port R3 DCR
Port R2 DCR
Port R1 DCR
Port R0 DCR
Port D8 DCR
Port D4 to D7 DCR
Port D0 to D3 DCR
System clock select register
Serial mode register B
Edge sense select register 2
Edge sense select register 1
Port mode register C
Port mode register B
LCD output register 3
LCD mode register
LCD control register
A/D data register upper
A/D data register lower
A/D mode register
Timer mode register D2
Timer mode register C2
Timer mode register B2
Timer-D
Timer mode register D1
Timer-C
Timer mode register C1
Miscellaneous register
Timer-B
Timer mode register B1
Timer mode register A
Serial data register upper
Serial data register lower
Serial mode register A
Port mode register A
$03F
$037
$036
$033
$032
$031
$030
$02E
$02D
$02C
$029
$028
$027
$026
$025
$024
$023
$020
$01F
$01C
$01B
$018
$017
$016
$015
$014
$013
$012
$011
$010
$00F
$00E
$00D
$00C
$00B
$00A
$009
$008
$007
$006
$005
$004
$003
$000
Register flag area
(V)
(DCR7)
(DCR6)
(DCR3)
(DCR2)
(DCR1)
(DCR0)
(DCD2)
(DCD1)
(DCD0)
(SSR)
(SMRB)
(ESR2)
(ESR1)
(PMRC)
(PMRB)
(LOR3)
(LMR)
(LCR)
(ADRU)
(ADRL)
(AMR)
(TMD2)
(TMC2)
(TMB2)
(TRDU/TWDU)
(TRDL/TWDL)
(TMD1)
(TRCU/TWCU)
(TRCL/TWCL)
(TMC1)
(MIS)
(TRBU/TWBU)
(TRBL/TWBL)
(TMB1)
(TMA)
(SRU)
(SRL)
(SMRA)
(PMRA)
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
W
W
Timer read register B lower
Timer read register B upper
Timer write register B lower
Timer write register B upper
$00A
$00B
10
11
Timer read register C lower
Timer read register C upper
Timer write register C lower
Timer write register C upper
$00E
$00F
14
15
Timer read register D lower
Timer read register D upper
Timer write register D lower
Timer write register D upper
(TRBL)
(TRBU)
R
R
(TWBL)
(TWBU)
W
W
(TRCL)
(TRCU)
R
R
(TWCL)
(TWCU)
W
W
(TRDL)
(TRDU)
R
R
(TWDL)
(TWDU)
W
W
$011
$012
17
18
0
RAM mapped register
$000
Memory register (16 digits)
LCD display area (32 digits)
Data (144 digits)
Stack (64 digits)
Data (464 digits
×
2)
V = 0 (bank 0)
V = 1 (bank 1)
64
80
$050
92
$05C
124
$07C
144
$090
608
$260
752
$2F0
960
$3C0
1023
$3FF
Data
(464 digits)
V = 0
(bank = 0)
Data
(464 digits)
V = 1
(bank = 1)
$090
$25F
The data area has two banks:
bank 0 (V = 0) and bank 1 (V = 1)
1.
$040
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
*
2
Read only
Write only
Read/write
R:
W:
R/W:
Notes:
HD4048412, HD404849, HD4074849
RAM mapped register
$000
Memory register (16 digits)
LCD display area (32 digits)
Stack (64 digits)
Data (400 digits)
$050
$05C
$07C
$090
$220
$3C0
$3FF
$040
Not used
Not used
HD404848
Not used
0
64
80
92
124
144
544
960
1023
*
1
Two registers are mapped to the
same address (at $00A, $00B,
$00E, $00F, $011, and $012)
2.
Figure 2 RAM Memory Map
相關(guān)PDF資料
PDF描述
HD404849H SPLICE
HD404849TF TERMINAL
HD4074849 TERMINAL
HD4074849FS CONTACT
HD4074849H CONTACT
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