參數(shù)資料
型號: HD404849FS
廠商: Hitachi,Ltd.
元件分類: 其它接口
英文描述: TERMINAL
中文描述: IGBT模塊
文件頁數(shù): 73/125頁
文件大?。?/td> 471K
代理商: HD404849FS
HD404849 Series
73
By selecting the input capture operation, pin R1
2
/TOD is set to R1
2
and timer D is reset to $00.
Registers for Timer D Operation:
By using the following registers, timer D operation modes are selected
and the timer D count is read and written.
Timer mode register D1 (TMD1: $010)
Timer mode register D2 (TMD2: $015)
Timer write register D (TWDL: $011, TWDU: $012)
Timer read register D (TRDL: $011, TRDU: $012)
Port mode register C (PMRC: $025)
Detection edge select register 2 (ESR2: $027)
Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and prescaler division ratio as shown in figure 59. It is reset to $0 by
MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. A timer D initialization by writing to
timer write register D (TWDL: $011, TWDU: $012) must be programmed to occur after a mode change
becomes valid.
When selecting the input capture timer operation, select the internal clock as the input clock source.
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HD404849H SPLICE
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