參數(shù)資料
型號: HD404849FS
廠商: Hitachi,Ltd.
元件分類: 其它接口
英文描述: TERMINAL
中文描述: IGBT模塊
文件頁數(shù): 62/125頁
文件大小: 471K
代理商: HD404849FS
HD404849 Series
62
Bit
Initial value
Read/Write
Bit name
3
0
W
TMB13
2
0
W
TMB12
0
0
W
TMB10
1
0
W
TMB11
Timer mode register B1 (TMB1: $009)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2048t
cyc
512t
cyc
128t
cyc
32t
cyc
8t
cyc
4t
cyc
2t
cyc
R1
3
/
EVNB
(external event input)
TMB12
TMB10
TMB11
Input clock period and input
clock source
TMB13
0
1
Free-running/reload
timer selection
Free-running timer
Reload timer
Figure 44 Timer Mode Register B1 (TMB1)
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. A timer B initialization by writing to timer write
register B (TWBL: $00A, TWBU: $00B) must be programmed to occur after a mode change becomes
valid.
Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output
mode as shown in figure 45. It is reset to $0 by MCU reset.
Bit
Initial value
Read/Write
Bit name
3
Not used
2
Not used
0
0
R/W
TMB20
1
0
R/W
TMB21
Timer mode register B2 (TMB2: $013)
TMB21
0
1
TMB20
0
1
0
1
R1
0
/TOB mode selection
R1
0
TOB
TOB
TOB
R1
0
port
Toggle output
0 output
1 output
Figure 45 Timer Mode Register B2 (TMB2)
Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of a lower digit
(TWBL) and upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit
value cannot be guaranteed. See figures 46 and 47.
相關PDF資料
PDF描述
HD404849H SPLICE
HD404849TF TERMINAL
HD4074849 TERMINAL
HD4074849FS CONTACT
HD4074849H CONTACT
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