參數(shù)資料
型號: HD404849FS
廠商: Hitachi,Ltd.
元件分類: 其它接口
英文描述: TERMINAL
中文描述: IGBT模塊
文件頁數(shù): 89/125頁
文件大?。?/td> 471K
代理商: HD404849FS
HD404849 Series
89
Bit
Initial value
Read/Write
Bit name
3
Not used
2
Not used
0
0
W
SMRB0
1
Undefined
W
SMRB1
SMRB0
0
1
Transmit clock division ratio
Prescaler output divided by 2
Prescaler output divided by 4
Serial mode register B (SMRB: $028)
SMRB1
0
1
Output level control in idle states
Low level
High level
Figure 71 Serial Mode Register B (SMRB)
Serial Data Register (SRL: $006, SRU: $007):
The serial data register configuration is shown in figures
72 and 73. This register has the following functions.
Transmission data write and shift
Receive data shift and read
Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the
transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 74.
Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.
Bit
Initial value
Read/Write
Bit name
3
Undefined
R/W
SR3
2
Undefined
R/W
SR2
0
Undefined
R/W
SR0
1
Undefined
R/W
SR1
Serial data register (lower digit) (SRL: $006)
Figure 72 Serial Data Register (SRL)
相關(guān)PDF資料
PDF描述
HD404849H SPLICE
HD404849TF TERMINAL
HD4074849 TERMINAL
HD4074849FS CONTACT
HD4074849H CONTACT
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