參數(shù)資料
型號： HCPL-316J
英文描述： 2.0 Amp Gate Drive Optocoupler with Integrated (V CE ) Desaturation Detection and Fault Status Feedback(帶集成不飽和檢測和誤差反饋的2.0 Amp門驅(qū)動耦合器)
中文描述： 2.0安培門極驅(qū)動光電耦合器與集成（五長官）飽和檢測與故障狀態(tài)反饋（帶集成不飽和檢測和誤差反饋的2.0安培門驅(qū)動耦合器）
文件頁數(shù)： 32/32頁
文件大小： 503K
代理商： HCPL-316J
Figure 80. Minimum LED Skew for Zero Dead Time.
Figure 81. Waveforms for Dead Time Calculation.
t
PHLMAX
t
PLHMIN
PDD* MAX = (t
PHL
-
t
PLH
)
MAX
= t
PHLMAX
-
t
PLHMIN
*PDD = PROPAGATION DELAY
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
V
IN+2
V
OUT2
V
IN+1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PLHMIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
PHLMAX
-
t
PHLMIN
) + (t
PLHMAX
-
t
PLHMIN
)
= (t
-
t
) – (t
PHLMIN
-
t
PLHMAX
)
= PDD*
MAX
– PDD*
MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
V
IN+2
V
OUT2
V
IN+1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PHLMIN
t
PHLMAX
t
PLHMAX
= PDD*
MAX
(t
PHL-
t
PLH
)
MAX
System Considerations
Propagation Delay Difference
(PDD)
The HCPL-316J includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in
Figure 62) are off. Any overlap in
Q1 and Q2 conduction will result
in large currents flowing through
the power devices between the
high and low voltage motor rails,
a potentially catastrophic condi-
tion that must be prevented.
To minimize dead time in a given
design, the turn-on of the
HCPL-316J driving Q2 should be
delayed (relative to the turn-off
of the HCPL-316J driving Q1) so
that under worst-case conditions,
transistor Q1 has just turned off
when transistor Q2 turns on, as
shown in Figure 80. The amount
of delay necessary to achieve this
condition is equal to the maxi-
mum value of the propagation
delay difference specification,
PDD
MAX
, which is specified to be
400 ns over the operating
temperature range of -40
°
C to
100
°
C.
Delaying the HCPL-316J turn-on
signals by the maximum
propagation delay difference
ensures that the minimum dead
time is zero, but it does not tell a
designer what the maximum dead
time will be. The maximum dead
time is equivalent to the
difference between the maximum
and minimum propagation delay
difference specifications as
shown in Figure 81. The
maximum dead time for the
HCPL-316J is 800 ns (= 400 ns -
(-400 ns)) over an operating
temperature range of -40
°
C to
100
°
C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal tempera-
tures and test conditions since
the optocouplers under consider-
ation are typically mounted in
close proximity to each other and
are switching identical IGBTs.
www.semiconductor.agilent.com
Data subject to change.
Copyright 1999 Agilent Technologies
Obsoletes 5966-2496E(4/98)
5968-5854E (11/99)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HCPL-316J#500 功能描述:邏輯輸出光電耦合器 2.0A IGBT Gate Drive RoHS:否 制造商:Fairchild Semiconductor 絕緣電壓:4243 Vrms 輸出類型:Push-Pull 最大傳播延遲時間:500 ns 最大正向二極管電壓: 最大反向二極管電壓: 最大正向二極管電流: 最大連續(xù)輸出電流:2.5 A 最大功率耗散:100 mW 最大工作溫度:+ 100 C 最小工作溫度:- 40 C 封裝 / 箱體:SO-16 封裝:Tube
HCPL-316J-000E 功能描述:邏輯輸出光電耦合器 2.0A IGBT Gate Drive RoHS:否 制造商:Fairchild Semiconductor 絕緣電壓:4243 Vrms 輸出類型:Push-Pull 最大傳播延遲時間:500 ns 最大正向二極管電壓: 最大反向二極管電壓: 最大正向二極管電流: 最大連續(xù)輸出電流:2.5 A 最大功率耗散:100 mW 最大工作溫度:+ 100 C 最小工作溫度:- 40 C 封裝 / 箱體:SO-16 封裝:Tube
HCPL-316J-000E 制造商:Avago Technologies 功能描述:GATE DRIVE OPTOCOUPLERLF - LEAD FREE VE
HCPL-316J-500E 功能描述:邏輯輸出光電耦合器 2.0A IGBT Gate Drive RoHS:否 制造商:Fairchild Semiconductor 絕緣電壓:4243 Vrms 輸出類型:Push-Pull 最大傳播延遲時間:500 ns 最大正向二極管電壓: 最大反向二極管電壓: 最大正向二極管電流: 最大連續(xù)輸出電流:2.5 A 最大功率耗散:100 mW 最大工作溫度:+ 100 C 最小工作溫度:- 40 C 封裝 / 箱體:SO-16 封裝:Tube
HCPL-3180 功能描述:高速光耦合器 2.0A IGBT Gate Drive RoHS:否 制造商:Avago Technologies 電流傳遞比: 最大波特率: 最大正向二極管電壓:1.75 V 最大反向二極管電壓:5 V 最大功率耗散:40 mW 最大工作溫度:+125 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-5 封裝:Tube
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