參數(shù)資料
型號: HCD404669
廠商: Hitachi,Ltd.
英文描述: Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit(帶雙音多頻電路的低電壓微計(jì)算機(jī))
中文描述: 低電壓如同在微機(jī)芯片的DTMF產(chǎn)生電路(帶雙音多頻電路的低電壓微計(jì)算機(jī))
文件頁數(shù): 81/142頁
文件大?。?/td> 894K
代理商: HCD404669
HD404669 Series
81
STS wait state
(Octal counter 1 = 000,
transmit clock disabled)
Transmit clock wait state
(Octal counter 1 = 000)
Trans
fer
state
(Octal counter 1 = 000)
MCU reset
00
SM1A write
04
STS instruction
01
Transmit clock
02
8 transmit clocks
03
STS instruction (IFS1 1)
05
SM1A write (IFS1 1)
06
External clock mode
STS wait state
(Octal counter 1 = 000,
transmit clock disabled)
Transmit clock wait state
(Octal counter 1 = 000)
Transfer state
(Octal counter 1 = 000)
SM1A write
14
STS instruction
11
Transmit clock
12
15
STS instruction (IFS1 1)
8 transmit clocks
13
Internal clock mode
Continuous clock output state
(PMRA 0, 1 = 00)
SM1A write
18
Transmit clock
17
16
Note: Refer to the Operating States section for the corresponding encircled numbers.
MCU reset
10
SM1A write (IFS1 1)
Figure 59 Serial Interface State Transitions
Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts the serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial
interface in transfer state. However, note that if continuous clock output mode is selected in internal
clock mode, the serial interface does not enter transfer state but enters continuous clock output state
(17).
The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04,
14) in transmit clock wait state.
Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.
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