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參數(shù)資料
| 型號： | HCD404669 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit(帶雙音多頻電路的低電壓微計算機) |
| 中文描述： | 低電壓如同在微機芯片的DTMF產(chǎn)生電路（帶雙音多頻電路的低電壓微計算機） |
| 文件頁數(shù)： | 71/142頁 |
| 文件大小： | 894K |
| 代理商： | HCD404669 |
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HD404669 Series
71
Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVND.
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by detection edge select register 2 (ESR2: $027).
When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:
$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 0) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing
0.
By selecting the input capture operation, pin R3
2
/TOD is set to R3
2
and timer D is reset to $00.
Registers for Timer D Operation:
By using the following registers, timer D operation modes are selected
and the timer D count is read and written.
Timer mode register D1 (TMD1: $010)
Timer mode register D2 (TMD2: $015)
Timer write register D (TWDL: $011, TWDU: $012)
Timer read register D (TRDL: $011, TRDU: $012)
Port mode register C (PMRC: $025)
Detection edge select register 2 (ESR2: $027)
Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 50. Timer mode
register D1 (TMD1: $010) is reset to $0 by an MCU reset or in stop mode.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by
writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change
becomes valid.
When selecting the input capture timer operation, select the internal clock as the input clock source.
When designating external event input for the input clock, set bit 1 (PMRC1) of port mode register C
(PMRC) to 1.
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