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參數(shù)資料
| 型號： | HC6094 |
| 廠商： | Intersil Corporation |
| 英文描述： | DRAM Memory IC; Memory Type:NMOS DRAM; Access Time, Tacc:200ns; Package/Case:16-DIP; Memory Configuration:4K x 1; Mounting Type:Through Hole |
| 中文描述： | ADSL模擬前端芯片 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 51K |
| 代理商： | HC6094 |
8
Pin Descriptions
PIN
NUMBER
PIN
NAME
PIN DESCRIPTION
43, 44
D13-D12
Digital Input bits 13 and 12. D13 is MSB.
1-12
D11-D0
Digital Input bits 11 thru 0. D0 is LSB.
13, 14
RXO
±
Receiver differential outputs.
15
VSSA_RX
Receiver -5V supply.
16
VDDA_RX
Receiver +5V supply.
17, 18
PGAI
±
PGA2 differential inputs.
19, 20
PGAO
±
PGA1 differential outputs.
21, 22
RXI
±
Receiver differential inputs (PGA1 inputs).
23
GNDA_RX
Receiver ground.
24
GNDD_RX
Serial interface ground.
25
SCLK
Serial interface clock pin.
26
RST
Serial interface reset pin.
27
SDI
Serial interface data input.
28
CS
Serial interface chip select.
29
VDDD_RX
Shift register Digital +5V supply.
30
ARTN
Analog return (ground).
31
VSSA_TX
Transmitter -5V supply.
32
VDDA_TX
Transmitter +5V supply.
33
VSSA_ATT
Attenuator -5V supply.
34, 35
TXO
±
Transmitter differential outputs.
36
VDDA_ATT
Attenuator +5V supply.
37
GNDA_TX
Analog ground for transmitter.
38
CTLOUT
Control Amplifier Output. Provides precision control of the current sources. Typically connected to
CTLIN.
39
CTLIN
Input to the Current Source Base Rail. Typically connected to CTLOUT. Requires a 0.1
μ
F capacitor
to VSSA_TX. Allows external decoupling of the current sources.
40
GNDD_TX
Digital Ground.
41
CLK
DAC input latch clock.
42
VDDD_TX
DAC digital +5V supply.
HC6094
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相關代理商/技術參數(shù) |
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|---|---|
| HC6094IN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HC-60T | 制造商:Taiyo Electric Ind. 功能描述: |
| HC6116JCHCT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HC6116JCHDT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HC6116JSHCT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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