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參數(shù)資料
| 型號(hào)： | HC6094 |
| 廠商： | Intersil Corporation |
| 英文描述： | DRAM Memory IC; Memory Type:NMOS DRAM; Access Time, Tacc:200ns; Package/Case:16-DIP; Memory Configuration:4K x 1; Mounting Type:Through Hole |
| 中文描述： | ADSL模擬前端芯片 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 51K |
| 代理商： | HC6094 |
6
Shift Register Format
Each write operation to a control register involves 16 bits of
data. The CS- signal must be enabled low during any serial
write operation. The data on SDI shall be clocked in during
the rising edge of SCLK. A3-A0 supply the address of the
control register, and D7-D0 supply the data.
Logic Timing Definitions
0
0
0
0
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D6
D7
CS-
SCLK
SDI
FIGURE 1. SERIAL CONTROL
CS
SCLK
t
2
t
3
SCLK
SDI
t
4
t
5
t
1
FIGURE 2. SERIAL INTERFACE
CLK
DAC DATA
t
S
t
H
FIGURE 3. DAC INTERFACE
HC6094
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PDF描述 |
|---|---|
| HC6616JCHZC | x8 ROM (Mask Programmable) |
| HC6616JCHZT | x8 ROM (Mask Programmable) |
| HC6616JSHZC | x8 ROM (Mask Programmable) |
| HC6616JSHZT | x8 ROM (Mask Programmable) |
| HC6616KCHZC | x8 ROM (Mask Programmable) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HC6094IN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HC-60T | 制造商:Taiyo Electric Ind. 功能描述: |
| HC6116JCHCT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HC6116JCHDT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HC6116JSHCT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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