9
FN4235.6
June 6, 2006
Figure 14 shows the relationship between the saturation
guard voltage, the loop current and the loop resistance.
Notice from Figure 14 that for a loop resistance <1.2k
(RSG
= 4.0k) the SLIC is operating in the constant current feed
region and for resistances >1.2k
the SLIC is operating in
the resistive feed region. Operation in the resistive feed
region allows long loop and off-hook transmission by
keeping the tip and ring voltages off the rails. Operation in
this region is transparent to the customer.
The Saturation Guard circuit (Figure 12) monitors the tip to
ring voltage via the transconductance amplifier A1. A1
generates a current that is proportional to the tip to ring
voltage difference. I1 is internally set to sink all of A1’s
current until the tip to ring voltage exceeds 12.5V. When the
tip to ring voltage exceeds 12.5V (with no RSG resistor) A1
supplies more current than I1 can sink. When this happens
A2 amplifies its input current by a factor of 12 and the current
through R1 becomes the difference between I2 and the
output current from A2. As the current from A2 increases, the
voltage across R1 decreases and the output voltage on RDC
decreases. This results in a corresponding decrease in the
loop current. The RSG pin provides the ability to increase the
saturation guard reference voltage beyond 12.5V. Equation
3 gives the relationship between the RSG resistor value and
the programmable saturation guard reference voltage:
where:
VSGREF = Saturation Guard reference voltage, and
RSG = Saturation Guard programming resistor.
When the Saturation guard reference voltage is exceeded,
the tip to ring voltage is calculated using Equation 4:
where:
VTR = Voltage differential between tip and ring, and
RL = Loop resistance.
For on-hook transmission RL = ∞, Equation 4 reduces to:
The value of RSG should be calculated to allow maximum
loop length operation. This requires that the saturation guard
reference voltage be set as high as possible without clipping
the incoming or outgoing VF signal. A voltage margin of -4V
HC5515
VTX
RRX
RDC1
RDC2
CDC
R
SN
RDC
IRSN
TIP
RING
-2.5V
IRING
ITIP
A2
ITIP
IRING
RSG
RSG
-5V
LOOP CURRENT
CIRCUIT
SATURATION GUARD
CIRCUIT
A1
I1
I2
R1
+
-
+
-
+
-
+
-
FIGURE 12. DC LOOP CURRENT
-5V
17.3k
01.2K
-50
-40
-30
-20
-10
0
VBAT = -48V, IL = 23mA, RSG = 4.0k
LOOP RESISTANCE (
)
VTIP
VRING
RESISTIVE FEED
REGION
TIP
TO
RI
NG
VOLT
AGE
(V)
CONSTANT CURRENT
FEED REGION
SATURATION
GUARD VOLTAGE
SATURATION
GUARD VOLTAGE
∞
FIGURE 13. VTR vs RL
0
10
20
30
0
10
20
30
40
50
LOOP CURRENT (mA)
T
IP
TO
RING
V
O
LT
AGE
(V
)
VBAT = -24V, RSG = ∞
VBAT = -48V, RSG = 4.0k
SATURATION GUARD
RESISTIVE FEED
REGION
CONSTANT CURRENT
FEED REGION
RSG = 4.0k
100k
100k
4k
1.5k
2k
700
<400
<1.2k
RL
RSG = ∞
VOLTAGE, VTR = 38V
SATURATION GUARD
VOLTAGE, VTR = 13V
FIGURE 14.
VTR vs IL and RL
V
SGREF
12.5
510
5
R
SG
17300
+
-----------------------------------
+
=
(EQ. 3)
V
TR
R
L
16.66
5
10
5
R
SG
17300
+
()
+
R
L
R
DC1
R
DC2
+
() 600
+
------------------------------------------------------------------------------------
×
=
(EQ. 4)
V
TR
16.66
510
5
R
SG
17300
+
-----------------------------------
+
=
(EQ. 5)
HC5515