參數(shù)資料
型號(hào)： GS8662Q18BD-357
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165
封裝： 15 X 13 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 2/36頁(yè)
文件大?。?/td> 850K
代理商： GS8662Q18BD-357
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 3
D0–D8
Byte 4
D9–D17
Written
Unchanged
Written
Beat 1
Beat 2
GS8662Q08/09/18/36BD-357/333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
10/36
2011, GSI Technology
Output Register Control
SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
相關(guān)PDF資料
PDF描述
GS8662Q18BGD-357IT 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165
GS8662Q18GE-167IT 4M X 18 STANDARD SRAM, 0.5 ns, PBGA165
GS8662R09BD-350 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165
GS8662R09BGD-400I 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8662Q18E-167 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q18E-167I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM
GS8662Q18E-200 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays
GS8662Q18E-200I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays
GS8662Q18E-250 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays
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