- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄173638 > GS8662Q18BD-357 (GSI TECHNOLOGY) 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 PDF資料下載
參數(shù)資料
| 型號： | GS8662Q18BD-357 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 850K |
| 代理商： | GS8662Q18BD-357 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
GS8662Q08/09/18/36BD-357/333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
23/36
2011, GSI Technology
Hold Times
Address Input Hold Time
tKHAX
0.28
—
0.28
—
0.30
—
0.35
—
0.4
—
ns
1
Control Input Hold Time (R, W)
tKHIX
0.28
—
0.28
—
0.30
—
0.35
—
0.4
—
ns
2
Control Input Hold Time (BWX) (BWX)
tKHIX
0.28
—
0.28
—
0.30
—
0.35
—
0.4
—
ns
3
Data Input Hold Time
tKHDX
0.28
—
0.28
—
0.30
—
0.35
—
0.4
—
ns
Notes:
1.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
2.
Control signals are R, W
3.
Control signals are BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
4.
If C, C are tied high, K, K become the references for C, C timing parameters
5.
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
6.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
7.
VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
8.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
AC Electrical Characteristics (Continued)
Parameter
Symbol
-357
-333
-300
-250
-200
Units Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
相關PDF資料 |
PDF描述 |
|---|---|
| GS8662Q18BGD-357IT | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662Q18GE-167IT | 4M X 18 STANDARD SRAM, 0.5 ns, PBGA165 |
| GS8662R09BD-350 | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662R09BGD-400I | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS88037BT-225I | 256K X 36 CACHE SRAM, 2.5 ns, PQFP100 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS8662Q18E-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q18E-167I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 2 SRAM |
| GS8662Q18E-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
| GS8662Q18E-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
| GS8662Q18E-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。