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參數資料
| 型號： | GS8662Q18GE-167IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 4M X 18 STANDARD SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件頁數： | 1/35頁 |
| 文件大小： | 1666K |
| 代理商： | GS8662Q18GE-167IT |
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GS8662Q08/09/18/36E-278/250/200/167
72Mb SigmaQuad-II
Burst of 2 SRAM
278 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.08 12/2007
1/35
2005, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Simultaneous Read and Write SigmaQuad Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write controls sampled at data-in time
Burst of 2 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
Pin-compatible with present 9Mb, 18Mb, and 36Mb and
future 144Mb devices
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaQuad Family Overview
The GSQ8662Q08/09/18/36E are built in compliance with
the SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Because Separate I/O SigmaQuad-II B2 RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read or
write transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a SigmaQuad-II B2 RAM is always one address pin
less than the advertised index depth (e.g., the 4M x 18 has a
2048K addressable index).
.
Parameter Synopsis
-278
-250
-200
-167
tKHKH
3.6 ns
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.5 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
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| GS880F36BGT-7.5T | 256K X 36 CACHE SRAM, 7.5 ns, PQFP100 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8662Q18GE-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
| GS8662Q18GE-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
| GS8662Q18GE-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
| GS8662Q18GE-250C | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
| GS8662Q18GE-250I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Trays |
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