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參數(shù)資料
| 型號： | GS8662D11BGD-400 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件頁數(shù)： | 33/34頁 |
| 文件大?。?/td> | 670K |
| 代理商： | GS8662D11BGD-400 |
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
8/34
2011, GSI Technology
GS8662D20/38BD-550/500/450/400/350
GS8662D06/11BD-500/450/400/350
Power-Up Sequence for SigmaQuad-II+ SRAMs
For compatibility across all vendors it is recommended that SigmaQuad-II+ SRAMs must be powered-up in a specific sequence in
order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at Low state.
1a. Apply VDD.
1b. Apply VDDQ.
1c. Apply VREF (may also be applied at the same time as VDDQ).
2. After voltages are within specification range, and clocks (K, K) are stablized, change Doff to High.
3. An additional 2048 clock cycles are required to lock the DLL after it has been enabled.
Note: The DLL may be reset by driving the Doff pin Low or by stopping the K clocks for at least 30 ns. 2048 cycles of clean
K clocks are always required to relock the DLL after it has been stabilized.
DLL Constraints
The DLL synchronizes to either K clock. These clocks should have Low phase jitter (tKVar).
The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired
operating clock frequency.
If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause
undefined errors or failures during the initial stage.
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 2048 cycles is required for DLL lock.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4-beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NWx” may be substituted in all the discussion above.
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS8662D18BGD-300I | 制造商:GSI Technology 功能描述:GS8662D18BGD-300I - Trays |
| GS8662D18E-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D18E-167I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D18E-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D18E-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
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